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authorJosé Roberto de Souza <jose.souza@intel.com>2019-07-11 10:31:15 -0700
committerLucas De Marchi <lucas.demarchi@intel.com>2019-07-11 16:31:27 -0700
commita1c5f1510b3f39d57a6eaa9d75c70e5beaa952ff (patch)
tree0519e059df7260bb9ddab4ef3b72beb87577c578 /drivers/gpu/drm/i915/i915_reg.h
parent36ca5335f202bd54faf38b37fed1b99078e1839e (diff)
drm/i915/tgl: Update DPLL clock reference register
This register definition changed from ICL and has now another meaning. Use the right bits on TGL. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-22-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8277862bbbe..3ff659a180e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9944,6 +9944,7 @@ enum skl_power_gate {
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
#define _ICL_DPLL0_CFGCR0 0x164000