diff options
author | Varun Wadekar <vwadekar@nvidia.com> | 2012-04-07 01:52:57 +0530 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-04-07 01:52:57 +0530 |
commit | 97caf63d0c837f9b5c9f6f469979e68c0378e83f (patch) | |
tree | c6fc834bcfb66268f474324eca619db419010532 /drivers/crypto | |
parent | 6a1a6f4f69adf0febfd923795b45edeff63e75ed (diff) |
Merge branch '3.4-rc1' into android-tegra-nv-3.3-rebased
Change-Id: Ib3b69ffc5ac3e07c9cc44cc49e9142088eec477e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'drivers/crypto')
-rw-r--r-- | drivers/crypto/Kconfig | 13 | ||||
-rw-r--r-- | drivers/crypto/caam/caamalg.c | 126 | ||||
-rw-r--r-- | drivers/crypto/caam/ctrl.c | 2 | ||||
-rw-r--r-- | drivers/crypto/geode-aes.c | 6 | ||||
-rw-r--r-- | drivers/crypto/hifn_795x.c | 13 | ||||
-rw-r--r-- | drivers/crypto/ixp4xx_crypto.c | 4 | ||||
-rw-r--r-- | drivers/crypto/mv_cesa.c | 12 | ||||
-rw-r--r-- | drivers/crypto/n2_core.c | 7 | ||||
-rw-r--r-- | drivers/crypto/omap-aes.c | 8 | ||||
-rw-r--r-- | drivers/crypto/omap-sham.c | 4 | ||||
-rw-r--r-- | drivers/crypto/padlock-aes.c | 9 | ||||
-rw-r--r-- | drivers/crypto/padlock-sha.c | 16 | ||||
-rw-r--r-- | drivers/crypto/picoxcell_crypto.c | 46 | ||||
-rw-r--r-- | drivers/crypto/s5p-sss.c | 6 | ||||
-rw-r--r-- | drivers/crypto/talitos.c | 1 | ||||
-rw-r--r-- | drivers/crypto/tegra-aes.c | 485 | ||||
-rw-r--r-- | drivers/crypto/tegra-aes.h | 123 |
17 files changed, 514 insertions, 367 deletions
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 0fc4e6fab404..65dec5463f1f 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -64,7 +64,6 @@ config CRYPTO_DEV_GEODE config ZCRYPT tristate "Support for PCI-attached cryptographic adapters" depends on S390 - select ZCRYPT_MONOLITHIC if ZCRYPT="y" select HW_RANDOM help Select this option if you want to use a PCI-attached cryptographic @@ -77,14 +76,6 @@ config ZCRYPT + Crypto Express3 Coprocessor (CEX3C) + Crypto Express3 Accelerator (CEX3A) -config ZCRYPT_MONOLITHIC - bool "Monolithic zcrypt module" - depends on ZCRYPT - help - Select this option if you want to have a single module z90crypt, - that contains all parts of the crypto device driver (ap bus, - request router and all the card drivers). - config CRYPTO_SHA1_S390 tristate "SHA1 digest algorithm" depends on S390 @@ -295,12 +286,14 @@ config CRYPTO_DEV_S5P config CRYPTO_DEV_TEGRA_AES tristate "Support for TEGRA AES hw engine" - depends on ARCH_TEGRA_2x_SOC || ARCH_TEGRA_3x_SOC + depends on ARCH_TEGRA select CRYPTO_AES select TEGRA_ARB_SEMAPHORE help TEGRA processors have AES module accelerator. Select this if you want to use the TEGRA module for AES algorithms. + To compile this driver as a module, choose M here: the module + will be called tegra-aes. config CRYPTO_DEV_TEGRA_SE tristate "Tegra SE driver for crypto algorithms" diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index e73cf2e8110a..534a36469d57 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -1844,6 +1844,25 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha224),cbc(aes))", + .driver_name = "authenc-hmac-sha224-cbc-aes-caam", + .blocksize = AES_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA224_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA224 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC, + }, + { .name = "authenc(hmac(sha256),cbc(aes))", .driver_name = "authenc-hmac-sha256-cbc-aes-caam", .blocksize = AES_BLOCK_SIZE, @@ -1864,6 +1883,26 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha384),cbc(aes))", + .driver_name = "authenc-hmac-sha384-cbc-aes-caam", + .blocksize = AES_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = AES_BLOCK_SIZE, + .maxauthsize = SHA384_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA384 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC, + }, + + { .name = "authenc(hmac(sha512),cbc(aes))", .driver_name = "authenc-hmac-sha512-cbc-aes-caam", .blocksize = AES_BLOCK_SIZE, @@ -1922,6 +1961,25 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha224),cbc(des3_ede))", + .driver_name = "authenc-hmac-sha224-cbc-des3_ede-caam", + .blocksize = DES3_EDE_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = DES3_EDE_BLOCK_SIZE, + .maxauthsize = SHA224_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA224 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC, + }, + { .name = "authenc(hmac(sha256),cbc(des3_ede))", .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam", .blocksize = DES3_EDE_BLOCK_SIZE, @@ -1942,6 +2000,25 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha384),cbc(des3_ede))", + .driver_name = "authenc-hmac-sha384-cbc-des3_ede-caam", + .blocksize = DES3_EDE_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = DES3_EDE_BLOCK_SIZE, + .maxauthsize = SHA384_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA384 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC, + }, + { .name = "authenc(hmac(sha512),cbc(des3_ede))", .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam", .blocksize = DES3_EDE_BLOCK_SIZE, @@ -2000,6 +2077,25 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha224),cbc(des))", + .driver_name = "authenc-hmac-sha224-cbc-des-caam", + .blocksize = DES_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = DES_BLOCK_SIZE, + .maxauthsize = SHA224_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA224 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC, + }, + { .name = "authenc(hmac(sha256),cbc(des))", .driver_name = "authenc-hmac-sha256-cbc-des-caam", .blocksize = DES_BLOCK_SIZE, @@ -2020,6 +2116,25 @@ static struct caam_alg_template driver_algs[] = { .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC, }, { + .name = "authenc(hmac(sha384),cbc(des))", + .driver_name = "authenc-hmac-sha384-cbc-des-caam", + .blocksize = DES_BLOCK_SIZE, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, + .geniv = "<built-in>", + .ivsize = DES_BLOCK_SIZE, + .maxauthsize = SHA384_DIGEST_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, + .class2_alg_type = OP_ALG_ALGSEL_SHA384 | + OP_ALG_AAI_HMAC_PRECOMP, + .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC, + }, + { .name = "authenc(hmac(sha512),cbc(des))", .driver_name = "authenc-hmac-sha512-cbc-des-caam", .blocksize = DES_BLOCK_SIZE, @@ -2205,7 +2320,8 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev, alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct caam_ctx); - alg->cra_flags = CRYPTO_ALG_ASYNC | template->type; + alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | + template->type; switch (template->type) { case CRYPTO_ALG_TYPE_ABLKCIPHER: alg->cra_type = &crypto_ablkcipher_type; @@ -2285,12 +2401,12 @@ static int __init caam_algapi_init(void) dev_warn(ctrldev, "%s alg registration failed\n", t_alg->crypto_alg.cra_driver_name); kfree(t_alg); - } else { + } else list_add_tail(&t_alg->entry, &priv->alg_list); - dev_info(ctrldev, "%s\n", - t_alg->crypto_alg.cra_driver_name); - } } + if (!list_empty(&priv->alg_list)) + dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n", + (char *)of_get_property(dev_node, "compatible", NULL)); return err; } diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 8ae3ba2a160d..c5f61c55d923 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -46,7 +46,7 @@ static int caam_remove(struct platform_device *pdev) /* Probe routine for CAAM top (controller) level */ static int caam_probe(struct platform_device *pdev) { - int d, ring, rspec; + int ring, rspec; struct device *dev; struct device_node *nprop, *np; struct caam_ctrl __iomem *ctrl; diff --git a/drivers/crypto/geode-aes.c b/drivers/crypto/geode-aes.c index 219d09cbb0d1..f3e36c86b6c3 100644 --- a/drivers/crypto/geode-aes.c +++ b/drivers/crypto/geode-aes.c @@ -393,7 +393,8 @@ static struct crypto_alg geode_cbc_alg = { .cra_driver_name = "cbc-aes-geode", .cra_priority = 400, .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_NEED_FALLBACK, + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, .cra_init = fallback_init_blk, .cra_exit = fallback_exit_blk, .cra_blocksize = AES_MIN_BLOCK_SIZE, @@ -479,7 +480,8 @@ static struct crypto_alg geode_ecb_alg = { .cra_driver_name = "ecb-aes-geode", .cra_priority = 400, .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | - CRYPTO_ALG_NEED_FALLBACK, + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, .cra_init = fallback_init_blk, .cra_exit = fallback_exit_blk, .cra_blocksize = AES_MIN_BLOCK_SIZE, diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c index fe765f49de58..c9c4befb5a8d 100644 --- a/drivers/crypto/hifn_795x.c +++ b/drivers/crypto/hifn_795x.c @@ -1731,9 +1731,9 @@ static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset while (size) { copy = min3(srest, dst->length, size); - daddr = kmap_atomic(sg_page(dst), KM_IRQ0); + daddr = kmap_atomic(sg_page(dst)); memcpy(daddr + dst->offset + offset, saddr, copy); - kunmap_atomic(daddr, KM_IRQ0); + kunmap_atomic(daddr); nbytes -= copy; size -= copy; @@ -1793,17 +1793,17 @@ static void hifn_process_ready(struct ablkcipher_request *req, int error) continue; } - saddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0); + saddr = kmap_atomic(sg_page(t)); err = ablkcipher_get(saddr, &t->length, t->offset, dst, nbytes, &nbytes); if (err < 0) { - kunmap_atomic(saddr, KM_SOFTIRQ0); + kunmap_atomic(saddr); break; } idx += err; - kunmap_atomic(saddr, KM_SOFTIRQ0); + kunmap_atomic(saddr); } hifn_cipher_walk_exit(&rctx->walk); @@ -2494,7 +2494,8 @@ static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t) t->drv_name, dev->name); alg->alg.cra_priority = 300; - alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; + alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; alg->alg.cra_blocksize = t->bsize; alg->alg.cra_ctxsize = sizeof(struct hifn_context); alg->alg.cra_alignmask = 0; diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 4c20c5bf6058..0053d7ebb5ca 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -265,7 +265,7 @@ static int setup_crypt_desc(void) BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64); crypt_virt = dma_alloc_coherent(dev, NPE_QLEN * sizeof(struct crypt_ctl), - &crypt_phys, GFP_KERNEL); + &crypt_phys, GFP_ATOMIC); if (!crypt_virt) return -ENOMEM; memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl)); @@ -1449,6 +1449,7 @@ static int __init ixp_module_init(void) /* block ciphers */ cra->cra_type = &crypto_ablkcipher_type; cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; if (!cra->cra_ablkcipher.setkey) cra->cra_ablkcipher.setkey = ablk_setkey; @@ -1461,6 +1462,7 @@ static int __init ixp_module_init(void) /* authenc */ cra->cra_type = &crypto_aead_type; cra->cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; cra->cra_aead.setkey = aead_setkey; cra->cra_aead.setauthsize = aead_setauthsize; diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c index 0d40cf66b3cc..e6ecc5f23943 100644 --- a/drivers/crypto/mv_cesa.c +++ b/drivers/crypto/mv_cesa.c @@ -899,7 +899,8 @@ struct crypto_alg mv_aes_alg_ecb = { .cra_name = "ecb(aes)", .cra_driver_name = "mv-ecb-aes", .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = 16, .cra_ctxsize = sizeof(struct mv_ctx), .cra_alignmask = 0, @@ -921,7 +922,8 @@ struct crypto_alg mv_aes_alg_cbc = { .cra_name = "cbc(aes)", .cra_driver_name = "mv-cbc-aes", .cra_priority = 300, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct mv_ctx), .cra_alignmask = 0, @@ -953,7 +955,8 @@ struct ahash_alg mv_sha1_alg = { .cra_driver_name = "mv-sha1", .cra_priority = 300, .cra_flags = - CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), .cra_init = mv_cra_hash_sha1_init, @@ -977,7 +980,8 @@ struct ahash_alg mv_hmac_sha1_alg = { .cra_driver_name = "mv-hmac-sha1", .cra_priority = 300, .cra_flags = - CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), .cra_init = mv_cra_hash_hmac_sha1_init, diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c index 8944dabc0e3c..67b97c5fd859 100644 --- a/drivers/crypto/n2_core.c +++ b/drivers/crypto/n2_core.c @@ -1402,7 +1402,8 @@ static int __devinit __n2_register_one_cipher(const struct n2_cipher_tmpl *tmpl) snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name); snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name); alg->cra_priority = N2_CRA_PRIORITY; - alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; + alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC; alg->cra_blocksize = tmpl->block_size; p->enc_type = tmpl->enc_type; alg->cra_ctxsize = sizeof(struct n2_cipher_context); @@ -1493,7 +1494,9 @@ static int __devinit __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl) snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name); snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name); base->cra_priority = N2_CRA_PRIORITY; - base->cra_flags = CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_NEED_FALLBACK; + base->cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_NEED_FALLBACK; base->cra_blocksize = tmpl->block_size; base->cra_ctxsize = sizeof(struct n2_hash_ctx); base->cra_module = THIS_MODULE; diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c index 5b970d9e9956..63e57b57a12c 100644 --- a/drivers/crypto/omap-aes.c +++ b/drivers/crypto/omap-aes.c @@ -756,7 +756,9 @@ static struct crypto_alg algs[] = { .cra_name = "ecb(aes)", .cra_driver_name = "ecb-aes-omap", .cra_priority = 100, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct omap_aes_ctx), .cra_alignmask = 0, @@ -776,7 +778,9 @@ static struct crypto_alg algs[] = { .cra_name = "cbc(aes)", .cra_driver_name = "cbc-aes-omap", .cra_priority = 100, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct omap_aes_ctx), .cra_alignmask = 0, diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c index 6399a8f1938a..a3fd6fc504b1 100644 --- a/drivers/crypto/omap-sham.c +++ b/drivers/crypto/omap-sham.c @@ -953,6 +953,7 @@ static struct ahash_alg algs[] = { .cra_driver_name = "omap-sha1", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, @@ -975,6 +976,7 @@ static struct ahash_alg algs[] = { .cra_driver_name = "omap-md5", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, @@ -998,6 +1000,7 @@ static struct ahash_alg algs[] = { .cra_driver_name = "omap-hmac-sha1", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, @@ -1022,6 +1025,7 @@ static struct ahash_alg algs[] = { .cra_driver_name = "omap-hmac-md5", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = SHA1_BLOCK_SIZE, diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c index 29b9469f8378..37b2e9406af6 100644 --- a/drivers/crypto/padlock-aes.c +++ b/drivers/crypto/padlock-aes.c @@ -19,6 +19,7 @@ #include <linux/percpu.h> #include <linux/smp.h> #include <linux/slab.h> +#include <asm/cpu_device_id.h> #include <asm/byteorder.h> #include <asm/processor.h> #include <asm/i387.h> @@ -503,12 +504,18 @@ static struct crypto_alg cbc_aes_alg = { } }; +static struct x86_cpu_id padlock_cpu_id[] = { + X86_FEATURE_MATCH(X86_FEATURE_XCRYPT), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id); + static int __init padlock_init(void) { int ret; struct cpuinfo_x86 *c = &cpu_data(0); - if (!cpu_has_xcrypt) + if (!x86_match_cpu(padlock_cpu_id)) return -ENODEV; if (!cpu_has_xcrypt_enabled) { diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c index 06bdb4b2c6a6..9266c0e25492 100644 --- a/drivers/crypto/padlock-sha.c +++ b/drivers/crypto/padlock-sha.c @@ -22,6 +22,7 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/scatterlist.h> +#include <asm/cpu_device_id.h> #include <asm/i387.h> struct padlock_sha_desc { @@ -526,6 +527,12 @@ static struct shash_alg sha256_alg_nano = { } }; +static struct x86_cpu_id padlock_sha_ids[] = { + X86_FEATURE_MATCH(X86_FEATURE_PHE), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids); + static int __init padlock_init(void) { int rc = -ENODEV; @@ -533,15 +540,8 @@ static int __init padlock_init(void) struct shash_alg *sha1; struct shash_alg *sha256; - if (!cpu_has_phe) { - printk(KERN_NOTICE PFX "VIA PadLock Hash Engine not detected.\n"); - return -ENODEV; - } - - if (!cpu_has_phe_enabled) { - printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n"); + if (!x86_match_cpu(padlock_sha_ids) || !cpu_has_phe_enabled) return -ENODEV; - } /* Register the newly added algorithm module if on * * VIA Nano processor, or else just do as before */ diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c index 58480d009324..410a03c01ca4 100644 --- a/drivers/crypto/picoxcell_crypto.c +++ b/drivers/crypto/picoxcell_crypto.c @@ -1322,6 +1322,7 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_driver_name = "cbc-aes-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = AES_BLOCK_SIZE, @@ -1349,6 +1350,7 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_driver_name = "ecb-aes-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), @@ -1373,7 +1375,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "cbc(des)", .cra_driver_name = "cbc-des-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), .cra_type = &crypto_ablkcipher_type, @@ -1398,7 +1402,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "ecb(des)", .cra_driver_name = "ecb-des-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), .cra_type = &crypto_ablkcipher_type, @@ -1422,7 +1428,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "cbc(des3_ede)", .cra_driver_name = "cbc-des3-ede-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES3_EDE_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), .cra_type = &crypto_ablkcipher_type, @@ -1447,7 +1455,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "ecb(des3_ede)", .cra_driver_name = "ecb-des3-ede-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES3_EDE_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), .cra_type = &crypto_ablkcipher_type, @@ -1472,7 +1482,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(sha1),cbc(aes))", .cra_driver_name = "authenc-hmac-sha1-cbc-aes-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1500,7 +1512,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(sha256),cbc(aes))", .cra_driver_name = "authenc-hmac-sha256-cbc-aes-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1527,7 +1541,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(md5),cbc(aes))", .cra_driver_name = "authenc-hmac-md5-cbc-aes-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1554,7 +1570,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", .cra_driver_name = "authenc-hmac-sha1-cbc-3des-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES3_EDE_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1582,7 +1600,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(sha256),cbc(des3_ede))", .cra_driver_name = "authenc-hmac-sha256-cbc-3des-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES3_EDE_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1609,7 +1629,9 @@ static struct spacc_alg ipsec_engine_algs[] = { .cra_name = "authenc(hmac(md5),cbc(des3_ede))", .cra_driver_name = "authenc-hmac-md5-cbc-3des-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_AEAD | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = DES3_EDE_BLOCK_SIZE, .cra_ctxsize = sizeof(struct spacc_aead_ctx), .cra_type = &crypto_aead_type, @@ -1639,7 +1661,9 @@ static struct spacc_alg l2_engine_algs[] = { .cra_name = "f8(kasumi)", .cra_driver_name = "f8-kasumi-picoxcell", .cra_priority = SPACC_CRYPTO_ALG_PRIORITY, - .cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER | CRYPTO_ALG_ASYNC, + .cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = 8, .cra_ctxsize = sizeof(struct spacc_ablk_ctx), .cra_type = &crypto_ablkcipher_type, diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c index 3376bca200fc..bc986f806086 100644 --- a/drivers/crypto/s5p-sss.c +++ b/drivers/crypto/s5p-sss.c @@ -518,7 +518,8 @@ static struct crypto_alg algs[] = { .cra_driver_name = "ecb-aes-s5p", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | - CRYPTO_ALG_ASYNC, + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct s5p_aes_ctx), .cra_alignmask = 0x0f, @@ -538,7 +539,8 @@ static struct crypto_alg algs[] = { .cra_driver_name = "cbc-aes-s5p", .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | - CRYPTO_ALG_ASYNC, + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct s5p_aes_ctx), .cra_alignmask = 0x0f, diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index 2d8c78901686..dc641c796526 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -2648,6 +2648,7 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev, alg->cra_priority = TALITOS_CRA_PRIORITY; alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct talitos_ctx); + alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY; t_alg->dev = dev; diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c index 6a5b5655a486..b07add67fe92 100644 --- a/drivers/crypto/tegra-aes.c +++ b/drivers/crypto/tegra-aes.c @@ -1,9 +1,18 @@ /* * drivers/crypto/tegra-aes.c * - * aes driver for NVIDIA tegra aes hardware + * Driver for NVIDIA Tegra AES hardware engines residing inside the + * Bit Stream Engine for Video (BSEV) and Bit Stream Engine for Audio + * (BSEA) hardware blocks. * - * Copyright (c) 2010-2011, NVIDIA Corporation. + * The programming sequence for these engines is with the help + * of commands which travel via a command queue residing between the + * CPU and the BSEV/A block. The BSEV engine has an internal RAM (VRAM) + * where the final input plaintext, keys and the IV have to be copied + * before starting the encrypt/decrypt operation. The BSEA engine operates + * with the help of IRAM. + * + * Copyright (c) 2010, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,14 +53,14 @@ #include "tegra-aes.h" -#define FLAGS_MODE_MASK 0x00ff -#define FLAGS_ENCRYPT BIT(0) -#define FLAGS_CBC BIT(1) -#define FLAGS_GIV BIT(2) -#define FLAGS_RNG BIT(3) -#define FLAGS_OFB BIT(4) -#define FLAGS_INIT BIT(5) -#define FLAGS_BUSY 1 +#define FLAGS_MODE_MASK 0x00FF +#define FLAGS_ENCRYPT BIT(0) +#define FLAGS_CBC BIT(1) +#define FLAGS_GIV BIT(2) +#define FLAGS_RNG BIT(3) +#define FLAGS_OFB BIT(4) +#define FLAGS_INIT BIT(5) +#define FLAGS_BUSY 1 /* * Defines AES engine Max process bytes size in one go, which takes 1 msec. @@ -92,35 +101,34 @@ #define ICQBITSHIFT_BLKCNT 0 /* memdma_vd command */ -#define MEMDMA_DIR_DTOVRAM 0 -#define MEMDMA_DIR_VTODRAM 1 -#define MEMDMABITSHIFT_DIR 25 -#define MEMDMABITSHIFT_NUM_WORDS 12 +#define MEMDMA_DIR_DTOVRAM 0 /* sdram -> vram */ +#define MEMDMA_DIR_VTODRAM 1 /* vram -> sdram */ +#define MEMDMA_DIR_SHIFT 25 +#define MEMDMA_NUM_WORDS_SHIFT 12 -/* Define AES Interactive command Queue commands Bit positions */ +/* command queue bit shifts */ enum { - ICQBITSHIFT_KEYTABLEADDR = 0, - ICQBITSHIFT_KEYTABLEID = 17, - ICQBITSHIFT_VRAMSEL = 23, - ICQBITSHIFT_TABLESEL = 24, - ICQBITSHIFT_OPCODE = 26, + CMDQ_KEYTABLEADDR_SHIFT = 0, + CMDQ_KEYTABLEID_SHIFT = 17, + CMDQ_VRAMSEL_SHIFT = 23, + CMDQ_TABLESEL_SHIFT = 24, + CMDQ_OPCODE_SHIFT = 26, }; -/* Define Ucq opcodes required for AES operation */ +/* Define commands required for AES operation */ enum { - UCQOPCODE_BLKSTARTENGINE = 0x0E, - UCQOPCODE_DMASETUP = 0x10, - UCQOPCODE_DMACOMPLETE = 0x11, - UCQOPCODE_SETTABLE = 0x15, - UCQOPCODE_MEMDMAVD = 0x22, + CMD_BLKSTARTENGINE = 0x0E, + CMD_DMASETUP = 0x10, + CMD_DMACOMPLETE = 0x11, + CMD_SETTABLE = 0x15, + CMD_MEMDMAVD = 0x22, }; -/* Define Aes command values */ +/* Define sub-commands */ enum { - UCQCMD_VRAM_SEL = 0x1, - UCQCMD_CRYPTO_TABLESEL = 0x3, - UCQCMD_KEYSCHEDTABLESEL = 0x4, - UCQCMD_KEYTABLESEL = 0x8, + SUBCMD_VRAM_SEL = 0x1, + SUBCMD_CRYPTO_TABLE_SEL = 0x3, + SUBCMD_KEY_TABLE_SEL = 0x8, }; #define UCQCMD_KEYTABLEADDRMASK 0x1FFFF @@ -134,6 +142,10 @@ struct tegra_aes_slot { bool available; }; +static struct tegra_aes_slot ssk = { + .slot_num = SSK_SLOT_NUM, +}; + struct tegra_aes_reqctx { unsigned long mode; }; @@ -199,7 +211,7 @@ struct tegra_aes_ctx { static struct tegra_aes_ctx rng_ctx; /* keep registered devices data here */ -static LIST_HEAD(slot_list); +static struct list_head dev_list; static DEFINE_SPINLOCK(list_lock); /* Engine specific work queues */ @@ -338,88 +350,70 @@ static int aes_start_crypt(struct tegra_aes_engine *eng, u32 in_addr, start: do { - value = aes_readl(eng, INTR_STATUS); + value = aes_readl(eng, TEGRA_AES_INTR_STATUS); eng_busy = value & BIT(0); icq_empty = value & BIT(3); } while (eng_busy || (!icq_empty)); - aes_writel(eng, 0xFFFFFFFF, INTR_STATUS); + aes_writel(eng, 0xFFFFFFFF, TEGRA_AES_INTR_STATUS); - /* error, dma xfer complete */ - aes_writel(eng, 0x33, INT_ENB); + /* enable error, dma xfer complete interrupts */ + aes_writel(eng, 0x33, TEGRA_AES_INT_ENB); enable_irq(eng->irq); - cmdq[qlen++] = UCQOPCODE_DMASETUP << ICQBITSHIFT_OPCODE; - cmdq[qlen++] = in_addr; - cmdq[qlen++] = UCQOPCODE_BLKSTARTENGINE << ICQBITSHIFT_OPCODE | - (nblocks-1) << ICQBITSHIFT_BLKCNT; - cmdq[qlen++] = UCQOPCODE_DMACOMPLETE << ICQBITSHIFT_OPCODE; + cmdq[0] = CMD_DMASETUP << CMDQ_OPCODE_SHIFT; + cmdq[1] = in_addr; + cmdq[2] = CMD_BLKSTARTENGINE << CMDQ_OPCODE_SHIFT | (nblocks-1); + cmdq[3] = CMD_DMACOMPLETE << CMDQ_OPCODE_SHIFT; - value = aes_readl(eng, CMDQUE_CONTROL); + value = aes_readl(eng, TEGRA_AES_CMDQUE_CONTROL); /* access SDRAM through AHB */ - value &= (~CMDQ_CTRL_SRC_STM_SEL_FIELD & ~CMDQ_CTRL_DST_STM_SEL_FIELD); - value |= (CMDQ_CTRL_SRC_STM_SEL_FIELD | CMDQ_CTRL_DST_STM_SEL_FIELD | - CMDQ_CTRL_ICMDQEN_FIELD | CMDQ_CTRL_ERROR_FLUSH_ENB); - aes_writel(eng, value, CMDQUE_CONTROL); + value &= ~TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD; + value &= ~TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD; + value |= TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD | + TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD | + TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD; + aes_writel(eng, value, TEGRA_AES_CMDQUE_CONTROL); + dev_dbg(dd->dev, "cmd_q_ctrl=0x%x", value); + + value = (0x1 << TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT) | + ((eng->ctx->keylen * 8) << + TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT) | + ((u32)upd_iv << TEGRA_AES_SECURE_IV_SELECT_SHIFT); - value = 0; if (mode & FLAGS_CBC) { - value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) | - ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) | - ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) | - (((mode & FLAGS_ENCRYPT) ? 2 : 3) - << SECURE_XOR_POS_SHIFT) | - (0 << SECURE_INPUT_SEL_SHIFT) | + value |= ((((mode & FLAGS_ENCRYPT) ? 2 : 3) + << TEGRA_AES_SECURE_XOR_POS_SHIFT) | (((mode & FLAGS_ENCRYPT) ? 2 : 3) - << SECURE_VCTRAM_SEL_SHIFT) | + << TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT) | ((mode & FLAGS_ENCRYPT) ? 1 : 0) - << SECURE_CORE_SEL_SHIFT | - (0 << SECURE_RNG_ENB_SHIFT) | - (0 << SECURE_HASH_ENB_SHIFT)); + << TEGRA_AES_SECURE_CORE_SEL_SHIFT); } else if (mode & FLAGS_OFB) { - value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) | - ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) | - ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) | - ((u32)0 << SECURE_IV_SELECT_SHIFT) | - (SECURE_XOR_POS_FIELD) | - (2 << SECURE_INPUT_SEL_SHIFT) | - (0 << SECURE_VCTRAM_SEL_SHIFT) | - (SECURE_CORE_SEL_FIELD) | - (0 << SECURE_RNG_ENB_SHIFT) | - (0 << SECURE_HASH_ENB_SHIFT)); - } else if (mode & FLAGS_RNG){ - value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) | - ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) | - ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) | - (0 << SECURE_XOR_POS_SHIFT) | - (0 << SECURE_INPUT_SEL_SHIFT) | - ((mode & FLAGS_ENCRYPT) ? 1 : 0) - << SECURE_CORE_SEL_SHIFT | - (1 << SECURE_RNG_ENB_SHIFT) | - (0 << SECURE_HASH_ENB_SHIFT)); + value |= ((TEGRA_AES_SECURE_XOR_POS_FIELD) | + (2 << TEGRA_AES_SECURE_INPUT_SEL_SHIFT) | + (TEGRA_AES_SECURE_CORE_SEL_FIELD)); + } else if (mode & FLAGS_RNG) { + value |= (((mode & FLAGS_ENCRYPT) ? 1 : 0) + << TEGRA_AES_SECURE_CORE_SEL_SHIFT | + TEGRA_AES_SECURE_RNG_ENB_FIELD); } else { - value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) | - ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) | - ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) | - (0 << SECURE_XOR_POS_SHIFT) | - (0 << SECURE_INPUT_SEL_SHIFT) | - (((mode & FLAGS_ENCRYPT) ? 1 : 0) - << SECURE_CORE_SEL_SHIFT) | - (0 << SECURE_RNG_ENB_SHIFT) | - (0 << SECURE_HASH_ENB_SHIFT)); + value |= (((mode & FLAGS_ENCRYPT) ? 1 : 0) + << TEGRA_AES_SECURE_CORE_SEL_SHIFT); } - aes_writel(eng, value, SECURE_INPUT_SELECT); - aes_writel(eng, out_addr, SECURE_DEST_ADDR); + dev_dbg(dd->dev, "secure_in_sel=0x%x", value); + aes_writel(eng, value, TEGRA_AES_SECURE_INPUT_SELECT); + + aes_writel(eng, out_addr, TEGRA_AES_SECURE_DEST_ADDR); INIT_COMPLETION(eng->op_complete); - for (i = 0; i < qlen - 1; i++) { + for (i = 0; i < AES_HW_MAX_ICQ_LENGTH; i++) { do { - value = aes_readl(eng, INTR_STATUS); - eng_busy = value & BIT(0); - icq_empty = value & BIT(3); + value = aes_readl(eng, TEGRA_AES_INTR_STATUS); + eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; + icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; } while (eng_busy || (!icq_empty)); - aes_writel(eng, cmdq[i], ICMDQUE_WR); + aes_writel(eng, cmdq[i], TEGRA_AES_ICMDQUE_WR); } ret = wait_for_completion_timeout(&eng->op_complete, @@ -432,7 +426,7 @@ start: } disable_irq(eng->irq); - aes_writel(eng, cmdq[qlen - 1], ICMDQUE_WR); + aes_writel(eng, cmdq[AES_HW_MA_ICQ_LENGTH - 1], TEGRA_AES_ICMDQUE_WR); if ((eng->status != 0) && (retries-- > 0)) { qlen = 0; @@ -442,32 +436,35 @@ start: return 0; } -static void aes_release_key_slot(struct tegra_aes_ctx *ctx) +static void aes_release_key_slot(struct tegra_aes_slot *slot) { + if (slot->slot_num == SSK_SLOT_NUM) + return; + spin_lock(&list_lock); - ctx->slot->available = true; - ctx->slot = NULL; + list_add_tail(&slot->node, &dev_list); + slot = NULL; spin_unlock(&list_lock); } -static struct tegra_aes_slot *aes_find_key_slot(struct tegra_aes_dev *dd) +static struct tegra_aes_slot *aes_find_key_slot(void) { struct tegra_aes_slot *slot = NULL; - bool found = 0; + struct list_head *new_head; + int empty; spin_lock(&list_lock); - list_for_each_entry(slot, &slot_list, node) { - dev_dbg(dd->dev, "empty:%d, num:%d\n", slot->available, - slot->slot_num); - if (slot->available) { - slot->available = false; - found = 1; - break; - } + empty = list_empty(&dev_list); + if (!empty) { + slot = list_entry(&dev_list, struct tegra_aes_slot, node); + new_head = dev_list.next; + list_del(&dev_list); + dev_list.next = new_head->next; + dev_list.prev = NULL; } - spin_unlock(&list_lock); - return found ? slot : NULL; + + return slot; } static int aes_set_key(struct tegra_aes_engine *eng, int slot_num) @@ -482,15 +479,15 @@ static int aes_set_key(struct tegra_aes_engine *eng, int slot_num) } /* enable key schedule generation in hardware */ - value = aes_readl(eng, SECURE_CONFIG_EXT); - value &= ~SECURE_KEY_SCH_DIS_FIELD; - aes_writel(eng, value, SECURE_CONFIG_EXT); + value = aes_readl(eng, TEGRA_AES_SECURE_CONFIG_EXT); + value &= ~TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD; + aes_writel(eng, value, TEGRA_AES_SECURE_CONFIG_EXT); /* select the key slot */ - value = aes_readl(eng, SECURE_CONFIG); - value &= ~SECURE_KEY_INDEX_FIELD; - value |= (slot_num << SECURE_KEY_INDEX_SHIFT); - aes_writel(eng, value, SECURE_CONFIG); + value = aes_readl(eng, TEGRA_AES_SECURE_CONFIG); + value &= ~TEGRA_AES_SECURE_KEY_INDEX_FIELD; + value |= (slot_num << TEGRA_AES_SECURE_KEY_INDEX_SHIFT); + aes_writel(eng, value, TEGRA_AES_SECURE_CONFIG); if (slot_num == SSK_SLOT_NUM) goto out; @@ -500,34 +497,28 @@ static int aes_set_key(struct tegra_aes_engine *eng, int slot_num) memcpy(dd->bsev.ivkey_base, eng->ctx->key, eng->ctx->keylen); /* copy the key table from sdram to vram */ - cmdq[0] = 0; - cmdq[0] = UCQOPCODE_MEMDMAVD << ICQBITSHIFT_OPCODE | - (MEMDMA_DIR_DTOVRAM << MEMDMABITSHIFT_DIR) | - (AES_HW_KEY_TABLE_LENGTH_BYTES/sizeof(u32)) - << MEMDMABITSHIFT_NUM_WORDS; + cmdq[0] = CMD_MEMDMAVD << CMDQ_OPCODE_SHIFT | + MEMDMA_DIR_DTOVRAM << MEMDMA_DIR_SHIFT | + AES_HW_KEY_TABLE_LENGTH_BYTES / sizeof(u32) << + MEMDMA_NUM_WORDS_SHIFT; cmdq[1] = (u32)eng->ivkey_phys_base; - for (i = 0; i < ARRAY_SIZE(cmdq); i++) - aes_writel(eng, cmdq[i], ICMDQUE_WR); + + aes_writel(eng, cmdq[0], TEGRA_AES_ICMDQUE_WR); + aes_writel(eng, cmdq[1], TEGRA_AES_ICMDQUE_WR); + do { - value = aes_readl(eng, INTR_STATUS); - eng_busy = value & BIT(0); - icq_empty = value & BIT(3); - dma_busy = value & BIT(23); + value = aes_readl(eng, TEGRA_AES_INTR_STATUS); + eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; + icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; + dma_busy = value & TEGRA_AES_DMA_BUSY_FIELD; } while (eng_busy & (!icq_empty) & dma_busy); /* settable command to get key into internal registers */ - value = 0; - value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE | - UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL | - UCQCMD_VRAM_SEL << ICQBITSHIFT_VRAMSEL | - (UCQCMD_KEYTABLESEL | slot_num) - << ICQBITSHIFT_KEYTABLEID; - aes_writel(eng, value, ICMDQUE_WR); - do { - value = aes_readl(eng, INTR_STATUS); - eng_busy = value & BIT(0); - icq_empty = value & BIT(3); - } while (eng_busy & (!icq_empty)); + value = CMD_SETTABLE << CMDQ_OPCODE_SHIFT | + SUBCMD_CRYPTO_TABLE_SEL << CMDQ_TABLESEL_SHIFT | + SUBCMD_VRAM_SEL << CMDQ_VRAMSEL_SHIFT | + (SUBCMD_KEY_TABLE_SEL | slot_num) + << CMDQ_KEYTABLEID_SHIFT; } else { memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES); memcpy(dd->bsea.iram_virt, eng->ctx->key, eng->ctx->keylen); @@ -539,20 +530,20 @@ static int aes_set_key(struct tegra_aes_engine *eng, int slot_num) aes_writel(eng, 0, IRAM_ACCESS_CFG); /* settable command to get key into internal registers */ - value = 0; - value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE | - UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL | - (UCQCMD_KEYTABLESEL | slot_num) - << ICQBITSHIFT_KEYTABLEID | + value = CMD_SETTABLE << CMDQ_OPCODE_SHIFT | + SUBCMD_CRYPTO_TABLE_SEL << CMDQ_TABLESEL_SHIFT | + (SUBCMD_KEY_TABLE_SEL | slot_num) + << CMDQ_KEYTABLEID_SHIFT | dd->bsea.iram_phys >> 2; - aes_writel(eng, value, ICMDQUE_WR); - do { - value = aes_readl(eng, INTR_STATUS); - eng_busy = value & BIT(0); - icq_empty = value & BIT(3); - } while (eng_busy & (!icq_empty)); } + aes_writel(eng, value, TEGRA_AES_ICMDQUE_WR); + do { + value = aes_readl(eng, TEGRA_AES_INTR_STATUS); + eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; + icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD; + } while (eng_busy & (!icq_empty)); + out: return 0; } @@ -657,7 +648,7 @@ static int tegra_aes_handle_req(struct tegra_aes_engine *eng) addr_in = sg_dma_address(in_sg); addr_out = sg_dma_address(out_sg); - count = min((int)sg_dma_len(in_sg), (int)dma_max); + count = min_t(int, sg_dma_len(in_sg), dma_max); WARN_ON(sg_dma_len(in_sg) != sg_dma_len(out_sg)); nblocks = DIV_ROUND_UP(count, AES_BLOCK_SIZE); @@ -666,6 +657,7 @@ static int tegra_aes_handle_req(struct tegra_aes_engine *eng) dma_unmap_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE); dma_unmap_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE); + if (ret < 0) { dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret); goto out; @@ -691,7 +683,7 @@ out: } static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, - unsigned int keylen) + unsigned int keylen) { struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); struct tegra_aes_dev *dd = aes_dev; @@ -706,6 +698,7 @@ static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, if ((keylen != AES_KEYSIZE_128) && (keylen != AES_KEYSIZE_192) && (keylen != AES_KEYSIZE_256)) { dev_err(dd->dev, "unsupported key size\n"); + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } @@ -727,10 +720,12 @@ static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, if (key) { if (!ctx->slot) { - key_slot = aes_find_key_slot(dd); + key_slot = aes_find_key_slot(); if (!key_slot) { dev_err(dd->dev, "no empty slot\n"); - goto out; + tegra_arb_mutex_unlock(dd->bsev.res_id); + tegra_arb_mutex_unlock(dd->bsea.res_id); + return -ENOMEM; } ctx->slot = key_slot; } @@ -835,9 +830,8 @@ static int tegra_aes_crypt(struct ablkcipher_request *req, unsigned long mode) int bsev_busy; int bsea_busy; - dev_dbg(dd->dev, "nbytes: %d, enc: %d, cbc: %d, ofb: %d\n", req->nbytes, - !!(mode & FLAGS_ENCRYPT), - !!(mode & FLAGS_CBC), + dev_dbg(dd->dev, "nbytes: %d, enc: %d, cbc: %d, ofb: %d\n", + req->nbytes, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC), !!(mode & FLAGS_OFB)); rctx->mode = mode; @@ -875,6 +869,7 @@ static int tegra_aes_cbc_decrypt(struct ablkcipher_request *req) { return tegra_aes_crypt(req, FLAGS_CBC); } + static int tegra_aes_ofb_encrypt(struct ablkcipher_request *req) { return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_OFB); @@ -975,7 +970,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed, dd->flags = FLAGS_ENCRYPT | FLAGS_RNG; if (!ctx->slot) { - key_slot = aes_find_key_slot(dd); + key_slot = aes_find_key_slot(); if (!key_slot) { dev_err(dd->dev, "no empty slot\n"); return -ENOMEM; @@ -1024,6 +1019,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed, tmp[1] = tegra_chip_uid(); dt = (u8 *)tmp; } + memcpy(ctx->dt, dt, DEFAULT_RNG_BLK_SZ); out: @@ -1045,25 +1041,21 @@ static int tegra_aes_cra_init(struct crypto_tfm *tfm) void tegra_aes_cra_exit(struct crypto_tfm *tfm) { - struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm); + struct tegra_aes_ctx *ctx = + crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm); if (ctx && ctx->slot) - aes_release_key_slot(ctx); + aes_release_key_slot(ctx->slot); } static struct crypto_alg algs[] = { { .cra_name = "disabled_ecb(aes)", .cra_driver_name = "ecb-aes-tegra", - .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct tegra_aes_ctx), .cra_alignmask = 3, .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = tegra_aes_cra_init, - .cra_exit = tegra_aes_cra_exit, .cra_u.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, @@ -1074,15 +1066,10 @@ static struct crypto_alg algs[] = { }, { .cra_name = "disabled_cbc(aes)", .cra_driver_name = "cbc-aes-tegra", - .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct tegra_aes_ctx), .cra_alignmask = 3, .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = tegra_aes_cra_init, - .cra_exit = tegra_aes_cra_exit, .cra_u.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, @@ -1094,15 +1081,10 @@ static struct crypto_alg algs[] = { }, { .cra_name = "disabled_ofb(aes)", .cra_driver_name = "ofb-aes-tegra", - .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, .cra_blocksize = AES_BLOCK_SIZE, - .cra_ctxsize = sizeof(struct tegra_aes_ctx), .cra_alignmask = 3, .cra_type = &crypto_ablkcipher_type, - .cra_module = THIS_MODULE, - .cra_init = tegra_aes_cra_init, - .cra_exit = tegra_aes_cra_exit, .cra_u.ablkcipher = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, @@ -1114,13 +1096,9 @@ static struct crypto_alg algs[] = { }, { .cra_name = "disabled_ansi_cprng", .cra_driver_name = "rng-aes-tegra", - .cra_priority = 100, .cra_flags = CRYPTO_ALG_TYPE_RNG, .cra_ctxsize = sizeof(struct tegra_aes_ctx), .cra_type = &crypto_rng_type, - .cra_module = THIS_MODULE, - .cra_init = tegra_aes_cra_init, - .cra_exit = tegra_aes_cra_exit, .cra_u.rng = { .rng_make_random = tegra_aes_get_random, .rng_reset = tegra_aes_rng_reset, @@ -1136,19 +1114,17 @@ static int tegra_aes_probe(struct platform_device *pdev) struct resource *res[2]; int err = -ENOMEM, i = 0, j; - if (aes_dev) - return -EEXIST; - - dd = kzalloc(sizeof(struct tegra_aes_dev), GFP_KERNEL); + dd = devm_kzalloc(dev, sizeof(struct tegra_aes_dev), GFP_KERNEL); if (dd == NULL) { dev_err(dev, "unable to alloc data struct.\n"); - return -ENOMEM;; + return err; } + dd->dev = dev; platform_set_drvdata(pdev, dd); - dd->slots = kzalloc(sizeof(struct tegra_aes_slot) * AES_NR_KEYSLOTS, - GFP_KERNEL); + dd->slots = devm_kzalloc(dev, sizeof(struct tegra_aes_slot) * + AES_NR_KEYSLOTS, GFP_KERNEL); if (dd->slots == NULL) { dev_err(dev, "unable to alloc slot struct.\n"); goto out; @@ -1157,21 +1133,32 @@ static int tegra_aes_probe(struct platform_device *pdev) spin_lock_init(&dd->lock); crypto_init_queue(&dd->queue, TEGRA_AES_QUEUE_LENGTH); - /* Get the module base address */ - res[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!res[0] || !res[1]) { - dev_err(dev, "invalid resource type: base\n"); - err = -ENODEV; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, "Couldn't request MEM resource\n"); + return -ENODEV; + } + + dd->bsev.io_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!dd->bsev.io_base) { + dev_err(dev, "can't ioremap bsev register space\n"); + err = -ENOMEM; goto out; } - dd->bsev.phys_base = res[0]->start; - dd->bsev.io_base = ioremap(dd->bsev.phys_base, resource_size(res[0])); - dd->bsea.phys_base = res[1]->start; - dd->bsea.io_base = ioremap(dd->bsea.phys_base, resource_size(res[1])); - if (!dd->bsev.io_base || !dd->bsea.io_base) { - dev_err(dev, "can't ioremap phys_base\n"); + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, "Couldn't request MEM resource\n"); + return -ENODEV; + } + + dd->bsea.io_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!dd->bsea.io_base) { + dev_err(dev, "can't ioremap bsea register space\n"); err = -ENOMEM; goto out; } @@ -1251,9 +1238,9 @@ static int tegra_aes_probe(struct platform_device *pdev) } dd->bsev.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, - &dd->bsev.dma_buf_out, GFP_KERNEL); + &dd->bsev.dma_buf_out, GFP_KERNEL); dd->bsea.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, - &dd->bsea.dma_buf_out, GFP_KERNEL); + &dd->bsea.dma_buf_out, GFP_KERNEL); if (!dd->bsev.buf_out || !dd->bsea.buf_out) { dev_err(dev, "can not allocate dma-out buffer\n"); err = -ENOMEM; @@ -1271,40 +1258,59 @@ static int tegra_aes_probe(struct platform_device *pdev) } /* get the irq */ - dd->bsev.irq = INT_VDE_BSE_V; - err = request_irq(dd->bsev.irq, aes_bsev_irq, IRQF_TRIGGER_HIGH, - "tegra-aes", dd); + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(dev, "invalid resource type: IRQ\n"); + err = -ENODEV; + goto out; + } + dd->bsev.irq = res->start; + + err = devm_request_irq(dev, dd->bsev.irq, aes_bsev_irq, + IRQF_TRIGGER_HIGH | IRQF_SHARED, "tegra-aes", dd); if (err) { dev_err(dev, "request_irq failed fir BSEV Engine\n"); goto out; } - disable_irq(dd->bsev.irq); - dd->bsea.irq = INT_VDE_BSE_A; - err = request_irq(dd->bsea.irq, aes_bsea_irq, IRQF_TRIGGER_HIGH, - "tegra-aes", dd); + res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!res) { + dev_err(dev, "invalid resource type: IRQ\n"); + err = -ENODEV; + goto out; + } + dd->bsea.irq = res->start; + + err = devm_request_irq(dev, dd->bsea.irq, aes_bsea_irq, + IRQF_TRIGGER_HIGH | IRQF_SHARED, "tegra-aes", dd); if (err) { dev_err(dev, "request_irq failed for BSEA Engine\n"); goto out; } - disable_irq(dd->bsea.irq); + + INIT_LIST_HEAD(&dev_list); spin_lock_init(&list_lock); spin_lock(&list_lock); for (i = 0; i < AES_NR_KEYSLOTS; i++) { if (i == SSK_SLOT_NUM) continue; - dd->slots[i].available = true; dd->slots[i].slot_num = i; INIT_LIST_HEAD(&dd->slots[i].node); - list_add_tail(&dd->slots[i].node, &slot_list); + list_add_tail(&dd->slots[i].node, &dev_list); } spin_unlock(&list_lock); aes_dev = dd; - for (i = 0; i < ARRAY_SIZE(algs); i++) { INIT_LIST_HEAD(&algs[i].cra_list); + + algs[i].cra_priority = 300; + algs[i].cra_ctxsize = sizeof(struct tegra_aes_ctx); + algs[i].cra_module = THIS_MODULE; + algs[i].cra_init = tegra_aes_cra_init; + algs[i].cra_exit = tegra_aes_cra_exit; + err = crypto_register_alg(&algs[i]); if (err) goto out; @@ -1320,8 +1326,8 @@ out: free_iram(dd); if (dd->bsev.ivkey_base) { - dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base, - dd->bsev.ivkey_phys_base); + dma_free_coherent(dev, AES_HW_KEY_TABLE_LENGTH_BYTES, + dd->bsev.ivkey_base, dd->bsev.ivkey_phys_base); } if (dd->bsev.buf_in && dd->bsea.buf_in) { @@ -1338,11 +1344,6 @@ out: dd->bsea.buf_out, dd->bsea.dma_buf_out); } - if (dd->bsev.io_base && dd->bsea.io_base) { - iounmap(dd->bsev.io_base); - iounmap(dd->bsea.io_base); - } - if (dd->bsev.pclk) clk_put(dd->bsev.pclk); @@ -1358,18 +1359,9 @@ out: if (bsea_wq) destroy_workqueue(bsea_wq); - if (dd->bsev.irq) - free_irq(dd->bsev.irq, dd); - - if (dd->bsea.irq) - free_irq(dd->bsea.irq, dd); - spin_lock(&list_lock); - list_del(&slot_list); + list_del(&dev_list); spin_unlock(&list_lock); - - kfree(dd->slots); - kfree(dd); aes_dev = NULL; dev_err(dev, "%s: initialization failed.\n", __func__); @@ -1382,8 +1374,8 @@ static int __devexit tegra_aes_remove(struct platform_device *pdev) struct tegra_aes_dev *dd = platform_get_drvdata(pdev); int i; - if (!dd) - return -ENODEV; + for (i = 0; i < ARRAY_SIZE(algs); i++) + crypto_unregister_alg(&algs[i]); cancel_work_sync(&bsev_work); cancel_work_sync(&bsea_work); @@ -1392,12 +1384,9 @@ static int __devexit tegra_aes_remove(struct platform_device *pdev) free_irq(dd->bsev.irq, dd); free_irq(dd->bsea.irq, dd); spin_lock(&list_lock); - list_del(&slot_list); + list_del(&dev_list); spin_unlock(&list_lock); - for (i = 0; i < ARRAY_SIZE(algs); i++) - crypto_unregister_alg(&algs[i]); - free_iram(dd); dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base, dd->bsev.ivkey_phys_base); @@ -1410,41 +1399,33 @@ static int __devexit tegra_aes_remove(struct platform_device *pdev) dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_out, dd->bsea.dma_buf_out); - iounmap(dd->bsev.io_base); - iounmap(dd->bsea.io_base); clk_put(dd->bsev.iclk); clk_put(dd->bsev.pclk); clk_put(dd->bsea.pclk); - kfree(dd->slots); - kfree(dd); + aes_dev = NULL; return 0; } +static struct of_device_id tegra_aes_of_match[] __devinitdata = { + { .compatible = "nvidia,tegra20-aes", }, + { .compatible = "nvidia,tegra30-aes", }, + { }, +}; + static struct platform_driver tegra_aes_driver = { .probe = tegra_aes_probe, .remove = __devexit_p(tegra_aes_remove), .driver = { .name = "tegra-aes", .owner = THIS_MODULE, + .of_match_table = tegra_aes_of_match, }, }; -static int __init tegra_aes_mod_init(void) -{ - INIT_LIST_HEAD(&slot_list); - return platform_driver_register(&tegra_aes_driver); -} - -static void __exit tegra_aes_mod_exit(void) -{ - platform_driver_unregister(&tegra_aes_driver); -} - -module_init(tegra_aes_mod_init); -module_exit(tegra_aes_mod_exit); +module_platform_driver(tegra_aes_driver); -MODULE_DESCRIPTION("Tegra AES hw acceleration support."); +MODULE_DESCRIPTION("Tegra AES/OFB/CPRNG hw acceleration support."); MODULE_AUTHOR("NVIDIA Corporation"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/crypto/tegra-aes.h b/drivers/crypto/tegra-aes.h index 45696467cdfc..86784acd6ebe 100644 --- a/drivers/crypto/tegra-aes.h +++ b/drivers/crypto/tegra-aes.h @@ -19,82 +19,85 @@ #ifndef __CRYPTODEV_TEGRA_AES_H #define __CRYPTODEV_TEGRA_AES_H -#define ICMDQUE_WR 0x1000 -#define CMDQUE_CONTROL 0x1008 -#define INTR_STATUS 0x1018 -#define INT_ENB 0x1040 -#define CONFIG 0x1044 -#define IRAM_ACCESS_CFG 0x10A0 -#define SECURE_DEST_ADDR 0x1100 -#define SECURE_INPUT_SELECT 0x1104 -#define SECURE_CONFIG 0x1108 -#define SECURE_CONFIG_EXT 0x110C -#define SECURE_SECURITY 0x1110 -#define SECURE_HASH_RESULT0 0x1120 -#define SECURE_HASH_RESULT1 0x1124 -#define SECURE_HASH_RESULT2 0x1128 -#define SECURE_HASH_RESULT3 0x112C -#define SECURE_SEC_SEL0 0x1140 -#define SECURE_SEC_SEL1 0x1144 -#define SECURE_SEC_SEL2 0x1148 -#define SECURE_SEC_SEL3 0x114C -#define SECURE_SEC_SEL4 0x1150 -#define SECURE_SEC_SEL5 0x1154 -#define SECURE_SEC_SEL6 0x1158 -#define SECURE_SEC_SEL7 0x115C +#define TEGRA_AES_ICMDQUE_WR 0x1000 +#define TEGRA_AES_CMDQUE_CONTROL 0x1008 +#define TEGRA_AES_INTR_STATUS 0x1018 +#define TEGRA_AES_INT_ENB 0x1040 +#define TEGRA_AES_CONFIG 0x1044 +#define TEGRA_AES_IRAM_ACCESS_CFG 0x10A0 +#define TEGRA_AES_SECURE_DEST_ADDR 0x1100 +#define TEGRA_AES_SECURE_INPUT_SELECT 0x1104 +#define TEGRA_AES_SECURE_CONFIG 0x1108 +#define TEGRA_AES_SECURE_CONFIG_EXT 0x110C +#define TEGRA_AES_SECURE_SECURITY 0x1110 +#define TEGRA_AES_SECURE_HASH_RESULT0 0x1120 +#define TEGRA_AES_SECURE_HASH_RESULT1 0x1124 +#define TEGRA_AES_SECURE_HASH_RESULT2 0x1128 +#define TEGRA_AES_SECURE_HASH_RESULT3 0x112C +#define TEGRA_AES_SECURE_SEC_SEL0 0x1140 +#define TEGRA_AES_SECURE_SEC_SEL1 0x1144 +#define TEGRA_AES_SECURE_SEC_SEL2 0x1148 +#define TEGRA_AES_SECURE_SEC_SEL3 0x114C +#define TEGRA_AES_SECURE_SEC_SEL4 0x1150 +#define TEGRA_AES_SECURE_SEC_SEL5 0x1154 +#define TEGRA_AES_SECURE_SEC_SEL6 0x1158 +#define TEGRA_AES_SECURE_SEC_SEL7 0x115C /* interrupt status reg masks and shifts */ -#define DMA_BUSY_FIELD BIT(9) -#define ICQ_EMPTY_FIELD BIT(3) -#define ENGINE_BUSY_FIELD BIT(0) +#define TEGRA_AES_ENGINE_BUSY_FIELD BIT(0) +#define TEGRA_AES_ICQ_EMPTY_FIELD BIT(3) +#define TEGRA_AES_DMA_BUSY_FIELD BIT(9) /* secure select reg masks and shifts */ -#define SECURE_SEL0_KEYREAD_ENB0_FIELD BIT(0) +#define TEGRA_AES_SECURE_SEL0_KEYREAD_ENB0_FIELD BIT(0) /* secure config ext masks and shifts */ -#define SECURE_KEY_SCH_DIS_FIELD BIT(15) +#define TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD BIT(15) /* secure config masks and shifts */ -#define SECURE_KEY_INDEX_SHIFT 20 -#define SECURE_KEY_INDEX_FIELD (0x1F << SECURE_KEY_INDEX_SHIFT) -#define SECURE_BLOCK_CNT_FIELD (0xFFFFF) +#define TEGRA_AES_SECURE_KEY_INDEX_SHIFT 20 +#define TEGRA_AES_SECURE_KEY_INDEX_FIELD (0x1F << TEGRA_AES_SECURE_KEY_INDEX_SHIFT) +#define TEGRA_AES_SECURE_BLOCK_CNT_SHIFT 0 +#define TEGRA_AES_SECURE_BLOCK_CNT_FIELD (0xFFFFF << TEGRA_AES_SECURE_BLOCK_CNT_SHIFT) /* stream interface select masks and shifts */ -#define CMDQ_CTRL_DST_STM_SEL_FIELD BIT(5) -#define CMDQ_CTRL_SRC_STM_SEL_FIELD BIT(4) -#define CMDQ_CTRL_ERROR_FLUSH_ENB BIT(2) -#define CMDQ_CTRL_ICMDQEN_FIELD BIT(1) -#define CMDQ_CTRL_UCMDQEN_FIELD BIT(0) +#define TEGRA_AES_CMDQ_CTRL_UCMDQEN_FIELD BIT(0) +#define TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD BIT(1) +#define TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD BIT(4) +#define TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD BIT(5) -/* config regsiter masks and shifts */ -#define CONFIG_ENDIAN_ENB_FIELD BIT(10) -#define CONFIG_MODE_SEL_FIELD BIT(0) +/* config register masks and shifts */ +#define TEGRA_AES_CONFIG_ENDIAN_ENB_FIELD BIT(10) +#define TEGRA_AES_CONFIG_MODE_SEL_SHIFT 0 +#define TEGRA_AES_CONFIG_MODE_SEL_FIELD (0x1F << TEGRA_AES_CONFIG_MODE_SEL_SHIFT) /* extended config */ -#define SECURE_OFFSET_CNT_FIELD (0xFF << 24) -#define SECURE_KEYSCHED_GEN_FIELD BIT(15) +#define TEGRA_AES_SECURE_OFFSET_CNT_SHIFT 24 +#define TEGRA_AES_SECURE_OFFSET_CNT_FIELD (0xFF << TEGRA_AES_SECURE_OFFSET_CNT_SHIFT) +#define TEGRA_AES_SECURE_KEYSCHED_GEN_FIELD BIT(15) /* init vector select */ -#define SECURE_IV_SELECT_SHIFT 10 -#define SECURE_IV_SELECT_FIELD BIT(10) +#define TEGRA_AES_SECURE_IV_SELECT_SHIFT 10 +#define TEGRA_AES_SECURE_IV_SELECT_FIELD BIT(10) /* secure engine input */ -#define SECURE_INPUT_ALG_SEL_SHIFT 28 -#define SECURE_INPUT_ALG_SEL_FIELD (0xF << SECURE_INPUT_ALG_SEL_SHIFT) -#define SECURE_INPUT_KEY_LEN_SHIFT 16 -#define SECURE_INPUT_KEY_LEN_FIELD (0xFFF << SECURE_INPUT_KEY_LEN_SHIFT) -#define SECURE_RNG_ENB_SHIFT 11 -#define SECURE_RNG_ENB_FIELD BIT(11) -#define SECURE_CORE_SEL_SHIFT 9 -#define SECURE_CORE_SEL_FIELD BIT(9) -#define SECURE_VCTRAM_SEL_SHIFT 7 -#define SECURE_VCTRAM_SEL_FIELD (0x3 << SECURE_VCTRAM_SEL_SHIFT) -#define SECURE_INPUT_SEL_SHIFT 5 -#define SECURE_INPUT_SEL_FIELD (0x3 << SECURE_INPUT_SEL_SHIFT) -#define SECURE_XOR_POS_SHIFT 3 -#define SECURE_XOR_POS_FIELD (0x3 << SECURE_XOR_POS_SHIFT) -#define SECURE_HASH_ENB_SHIFT 2 -#define SECURE_HASH_ENB_FIELD BIT(2) -#define SECURE_ON_THE_FLY_FIELD BIT(0) +#define TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT 28 +#define TEGRA_AES_SECURE_INPUT_ALG_SEL_FIELD (0xF << TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT) +#define TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT 16 +#define TEGRA_AES_SECURE_INPUT_KEY_LEN_FIELD (0xFFF << TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT) +#define TEGRA_AES_SECURE_RNG_ENB_FIELD BIT(11) +#define TEGRA_AES_SECURE_CORE_SEL_SHIFT 9 +#define TEGRA_AES_SECURE_CORE_SEL_FIELD BIT(9) +#define TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT 7 +#define TEGRA_AES_SECURE_VCTRAM_SEL_FIELD (0x3 << TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT) +#define TEGRA_AES_SECURE_INPUT_SEL_SHIFT 5 +#define TEGRA_AES_SECURE_INPUT_SEL_FIELD (0x3 << TEGRA_AES_SECURE_INPUT_SEL_SHIFT) +#define TEGRA_AES_SECURE_XOR_POS_SHIFT 3 +#define TEGRA_AES_SECURE_XOR_POS_FIELD (0x3 << TEGRA_AES_SECURE_XOR_POS_SHIFT) +#define TEGRA_AES_SECURE_HASH_ENB_FIELD BIT(2) +#define TEGRA_AES_SECURE_ON_THE_FLY_FIELD BIT(0) + +/* interrupt error mask */ +#define TEGRA_AES_INT_ERROR_MASK 0xFFF000 #endif |