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authorLinus Torvalds <torvalds@linux-foundation.org>2015-11-02 11:40:22 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2015-11-02 11:40:22 -0800
commit17a1359034e1fb5cfe9e5196a8ab5153acfacdc6 (patch)
treee9b12d256183b9cbf4d95fbd5628cba725c7e531 /drivers/clk
parent66b019967845a5af58802fd9af77f2317e5298a1 (diff)
parent7cc8d580228cc712edcf7a1856a3bdb38c164e83 (diff)
Merge tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC updates from Ulf Hansson: "MMC core: - Add new API to set VCCQ voltage - mmc_regulator_set_vqmmc() - Add new ioctl to allow userspace to send multi commands - Wait for card busy signalling before starting SDIO requests - Remove MMC_CLKGATE - Enable tuning for DDR50 mode - Some code clean-up/improvements to mmc pwrseq - Use highest priority for eMMC restart handler - Add DT bindings for eMMC hardware reset support - Extend the mmc_send_tuning() API - Improve ios show for debugfs - A couple of code optimizations MMC host: - Some generic OF improvements - Various code clean-ups - sirf: Add support for DDR50 - sunxi: Add support for card busy detection - mediatek: Use MMC_CAP_RUNTIME_RESUME - mediatek: Add support for eMMC HW-reset - mediatek: Add support for HS400 - dw_mmc: Convert to use the new mmc_regulator_set_vqmmc() API - dw_mmc: Add external DMA interface support - dw_mmc: Some various improvements - dw_mmc-rockchip: MMC tuning with the clock phase framework - sdhci: Properly clear IRQs during resume - sdhci: Enable tuning for DDR50 mode - sdhci-of-esdhc: Use IRQ mode for card detection - sdhci-of-esdhc: Support both BE and LE host controller - sdhci-pci: Build o2micro support in the same module - sdhci-pci: Support for new Intel host controllers - sdhci-acpi: Support for new Intel host controllers" * tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc: (73 commits) mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register mmc: dw_mmc: NULL dereference in error message mmc: pwrseq: Use highest priority for eMMC restart handler mmc: mediatek: add HS400 support mmc: mmc: extend the mmc_send_tuning() mmc: mediatek: add implement of ops->hw_reset() mmc: mediatek: fix got GPD checksum error interrupt when data transfer mmc: mediatek: change the argument "ddr" to "timing" mmc: mediatek: make cmd_ints_mask to const mmc: dt-bindings: update Mediatek MMC bindings mmc: core: Add DT bindings for eMMC hardware reset support mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2 mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllers mmc: sdhci-pci: Add more PCI IDs for Intel controllers arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-mmc-phase.c54
1 files changed, 35 insertions, 19 deletions
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c
index 9b613426e968..bc24e5a002e7 100644
--- a/drivers/clk/rockchip/clk-mmc-phase.c
+++ b/drivers/clk/rockchip/clk-mmc-phase.c
@@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
#define PSECS_PER_SEC 1000000000000LL
/*
- * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
- * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
*/
#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
@@ -69,7 +69,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
- degrees += delay_num * factor / 10000;
+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
}
return degrees % 360;
@@ -82,25 +82,41 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
u8 nineties, remainder;
u8 delay_num;
u32 raw_value;
- u64 delay;
-
- /* allow 22 to be 22.5 */
- degrees++;
- /* floor to 22.5 increment */
- degrees -= ((degrees) * 10 % 225) / 10;
+ u32 delay;
nineties = degrees / 90;
- /* 22.5 multiples */
- remainder = (degrees % 90) / 22;
-
- delay = PSECS_PER_SEC;
- do_div(delay, rate);
- /* / 360 / 22.5 */
- do_div(delay, 16);
- do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
-
+ remainder = (degrees % 90);
+
+ /*
+ * Due to the inexact nature of the "fine" delay, we might
+ * actually go non-monotonic. We don't go _too_ monotonic
+ * though, so we should be OK. Here are options of how we may
+ * work:
+ *
+ * Ideally we end up with:
+ * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
+ *
+ * On one extreme (if delay is actually 44ps):
+ * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
+ * The other (if delay is actually 77ps):
+ * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
+ *
+ * It's possible we might make a delay that is up to 25
+ * degrees off from what we think we're making. That's OK
+ * though because we should be REALLY far from any bad range.
+ */
+
+ /*
+ * Convert to delay; do a little extra work to make sure we
+ * don't overflow 32-bit / 64-bit numbers.
+ */
+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
delay *= remainder;
- delay_num = (u8) min(delay, 255ULL);
+ delay = DIV_ROUND_CLOSEST(delay,
+ (rate / 1000) * 36 *
+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
+
+ delay_num = (u8) min_t(u32, delay, 255);
raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;