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authorPhil Elwell <phil@raspberrypi.org>2017-06-01 15:14:22 +0100
committerStephen Boyd <sboyd@codeaurora.org>2017-06-02 15:42:21 -0700
commit3542976d85d96ab83f6c5b3ff9fb483620c6ba47 (patch)
tree1df1d995833535dfd9840fa8172be1264a7ee1a4 /drivers/clk/versatile/clk-realview.c
parent8c0de581c4f590450a9e9850e8049f9313bb1e62 (diff)
clk: bcm2835: Minimise clock jitter for PCM clock
Fractional clock dividers generate accurate average frequencies but with jitter, particularly when the integer divisor is small. Introduce a new metric of clock accuracy to penalise clocks with a good average but worse jitter compared to clocks with an average which is no better but with lower jitter. The metric is the ideal rate minus the worse deviation from that ideal using the nearest integer divisors. Use this metric for parent selection for clocks requiring low jitter (currently just PCM). Signed-off-by: Phil Elwell <phil@raspberrypi.org> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/versatile/clk-realview.c')
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