diff options
| author | Thierry Reding <treding@nvidia.com> | 2016-04-08 15:16:28 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:54 +0200 |
| commit | f7c42d98621739d416cc4a739b721574fcbe910c (patch) | |
| tree | cbd6f61c1a1b90780e63e7be5c3c4d3bd0988b5e /drivers/clk/tegra/clk-dfll.h | |
| parent | e8f6a68c508b5d1cc4612ada028d87c74ab279d5 (diff) | |
clk: tegra: dfll: Properly clean up on failure and removal
Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-dfll.h')
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index d192982b1f96..ed2ad888268f 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -25,6 +25,7 @@ /** * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @dev: struct device * that holds the OPP table for the DFLL + * @max_freq: maximum frequency supported on this SoC * @cvb: CPU frequency table for this SoC * @init_clock_trimmers: callback to initialize clock trimmers * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage @@ -32,6 +33,7 @@ */ struct tegra_dfll_soc_data { struct device *dev; + unsigned long max_freq; const struct cvb_table *cvb; void (*init_clock_trimmers)(void); |