summaryrefslogtreecommitdiff
path: root/drivers/clk/sunxi-ng/ccu_phase.h
diff options
context:
space:
mode:
authorChen-Yu Tsai <wens@csie.org>2017-10-12 16:37:04 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-10-13 09:27:34 +0200
commitee6501d69217a887cb496c42ff97ba43adff4ab1 (patch)
tree8cc397672adf7e0adea9b5485fa03d9c32ed7523 /drivers/clk/sunxi-ng/ccu_phase.h
parent042f7f8f9715096abce42b944d4a23b0e3c31521 (diff)
clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using the closest clock rate possible with integer N-M factors. This resulted in audio playback being slightly slower than it should be. The vendor kernel gets around this (for newer SoCs) by using sigma-delta modulation to generate a fractional-N factor. As the PLL hardware is identical in most chips, we can back port the settings from the newer SoC, in this case the H3, onto the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_phase.h')
0 files changed, 0 insertions, 0 deletions