diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-11-11 09:08:59 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-11-13 17:32:22 +0800 |
| commit | d15f25651247ec5dac71a16f9ba7611b90759bea (patch) | |
| tree | 40e6599a64a00fa64676ce8a35694d0440a0868b /drivers/clk/imx | |
| parent | 05d0b49db684ca55df4cff3dc62d58eb1ba4c123 (diff) | |
MLK-24992-01 clk: imx8mp: Change system pll1/pll2 as fixed rate clock
when system running at ND mode, the noc, noc_io & gic clock can be sourced
from system PLL1, then system PLL2 will be disable during boot stage. it
seems disabling system PLL2 will lead to system hang due to unknow reason.
As the system PLL1/PLL2 should be used as fixed rate PLL, so simplify the
complexity of clock tree management, change these two PLLs as fixed rate clock.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers/clk/imx')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1f08e9e6dc12..328e5f6468fd 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -570,8 +570,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) clks[IMX8MP_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mp_gpu_pll); clks[IMX8MP_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mp_vpu_pll); clks[IMX8MP_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll); - clks[IMX8MP_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll); - clks[IMX8MP_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll); + clks[IMX8MP_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000); + clks[IMX8MP_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000); clks[IMX8MP_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll); /* PLL bypass out */ |