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authorGary King <gking@nvidia.com>2009-12-16 10:30:05 -0800
committerGary King <gking@nvidia.com>2009-12-16 19:01:10 -0800
commit4e46c6ed79a3f68cf8d30665398939f6592f58ae (patch)
treee58191b43ceb5a3afa1cb5467fefb2aefa3cc5ef /arch
parent27f4fe2cfbd8ffd5e80de5580753fbbf809a2b3f (diff)
tegra RM: promote RESET_KBC and RESET_SOC (ap15) to functions rather than macros
also use a volatile bool for the infinite loop in RESET_SOC in both ap15 and ap20 implementations, rather than the do-nothing for loop
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c59
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c3
2 files changed, 35 insertions, 27 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c
index 8c428b93f85a..4154c83e3d1b 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clocks.c
@@ -405,35 +405,42 @@ Ap15EnableTvDacClock(
} while( 0 )
// KBC reset is available in the pmc control register.
-#define RESET_KBC( rm, delay ) \
- do { \
- regaddr = (APBDEV_PMC_CNTRL_0); \
- NvOsMutexLock((rm)->CarMutex); \
- reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr); \
- reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, ENABLE, reg); \
- NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg); \
- if (Hold) \
- {\
- NvOsMutexUnlock((rm)->CarMutex); \
- break; \
- }\
- NvRmPrivWaitUS( (rm), (delay) ); \
- reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, DISABLE, reg); \
- NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg); \
- NvOsMutexUnlock((rm)->CarMutex); \
- } while( 0 )
+static void RESET_KBC(NvRmDeviceHandle rm, NvU32 delay, NvBool Hold)
+{
+ NvU32 reg;
+ NvU32 regaddr;
+
+ regaddr = (APBDEV_PMC_CNTRL_0);
+ NvOsMutexLock((rm)->CarMutex);
+ reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr);
+ reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, ENABLE, reg);
+ NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+ if (Hold)
+ {
+ NvOsMutexUnlock((rm)->CarMutex);
+ return;
+ }
+ NvRmPrivWaitUS( (rm), (delay) );
+ reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, KBC_RST, DISABLE, reg);
+ NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+ NvOsMutexUnlock((rm)->CarMutex);
+}
// Use PMC control to reset the entire SoC. Just wait forever after reset is
// issued - h/w would auto-clear it and restart SoC
-#define RESET_SOC( rm ) \
- do { \
- regaddr = (APBDEV_PMC_CNTRL_0); \
- reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr); \
- reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, MAIN_RST, ENABLE, reg); \
- NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg); \
- for (;;) ; \
- } while( 0 )
+static void RESET_SOC(NvRmDeviceHandle rm)
+{
+ NvU32 reg;
+ NvU32 regaddr;
+
+ volatile NvBool b = NV_TRUE;
+ regaddr = (APBDEV_PMC_CNTRL_0);
+ reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, regaddr);
+ reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, MAIN_RST, ENABLE, reg);
+ NV_REGW((rm), NvRmModuleID_Pmif, 0, regaddr, reg);
+ while (b) { ; }
+}
void AP15ModuleReset(
@@ -455,7 +462,7 @@ void AP15ModuleReset(
break;
case NvRmModuleID_Kbc:
NV_ASSERT( Instance == 0 );
- RESET_KBC(hDevice, NVRM_RESET_DELAY );
+ RESET_KBC(hDevice, NVRM_RESET_DELAY, Hold);
break;
case NvRmModuleID_SysStatMonitor:
NV_ASSERT( Instance == 0 );
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c
index ceb815f944c6..6c3b287a2f0f 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.c
@@ -575,11 +575,12 @@ NvRmPrivAp20SetPmuIrqPolarity(
// issued - h/w would auto-clear it and restart SoC
#define RESET_SOC( rm ) \
do { \
+ volatile NvBool b = NV_TRUE; \
NvU32 reg; \
reg = NV_REGR((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); \
reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, MAIN_RST, ENABLE, reg); \
NV_REGW((rm), NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, reg); \
- for (;;) ; \
+ while (b) { ; } \
} while( 0 )
void AP20ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold)