diff options
| author | David Schalig <dschalig@nvidia.com> | 2011-03-04 15:33:49 +0900 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-03-08 20:53:52 -0800 |
| commit | e70e51e6fe64a85281f1192fc9261a99022df8d5 (patch) | |
| tree | 07b31901e4cd78b1934e7fe24897fd91f67b1edd /arch | |
| parent | 04db8ee9121dbddcccfa5fb0e0e34b9a5028c6c3 (diff) | |
[Ventana/Whistler] Correct initial PLL_A freq
Initial PLL_A frequency setting was wrong in Ventana and Whistler
board files. It was working because bootloader initialized PLL_A
already.
Tested on Ventana, bug 798828
Change-Id: I3d0cf9d3afe336a1c8dd4b3144bab313beca011a
Reviewed-on: http://git-master/r/21603
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/board-ventana.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board-whistler.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index 1a8b70c3e4c1..ec4e044bfe66 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -235,7 +235,7 @@ static __initdata struct tegra_clk_init_table ventana_clk_init_table[] = { { "blink", "clk_32k", 32768, false}, { "pll_p_out4", "pll_p", 24000000, true }, { "pwm", "clk_32k", 32768, false}, - { "pll_a", NULL, 11289600, true}, + { "pll_a", NULL, 56448000, true}, { "pll_a_out0", NULL, 11289600, true}, { "i2s1", "pll_a_out0", 11289600, true}, { "i2s2", "pll_a_out0", 11289600, true}, diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 613c05814961..990afe0f1f53 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -140,7 +140,7 @@ static __initdata struct tegra_clk_init_table whistler_clk_init_table[] = { { "uartc", "pll_m", 600000000, false}, { "pwm", "clk_32k", 32768, false}, { "kbc", "clk_32k", 32768, true}, - { "pll_a", NULL, 11289600, true}, + { "pll_a", NULL, 56448000, true}, { "pll_a_out0", NULL, 11289600, true}, { "i2s1", "pll_a_out0", 11289600, true}, { "i2s2", "pll_a_out0", 11289600, true}, |