merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36

Conflicts:
	arch/arm/mach-tegra/Makefile
	arch/arm/mach-tegra/fuse.c
	arch/arm/mach-tegra/fuse.h
	arch/arm/mach-tegra/kfuse.c
	arch/arm/mach-tegra/tegra2_clocks.c
	drivers/video/tegra/dc/Makefile
	drivers/video/tegra/dc/hdmi.c
	drivers/video/tegra/dc/hdmi.h
	drivers/video/tegra/dc/nvhdcp.c

Change-Id: I60a025d9e23e0699afcfaf9e3e42a98263cd7de8

6 files changed, 32 insertions, 3 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd2c427f0e2b..0a293ee4a313 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1129,6 +1129,16 @@ config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption of the
 	  processor.
 
+config ARM_ERRATA_720791
+	bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the 720791 Cortex-A9
+	  (r1p0..r1p2) erratum.  The Jazelle instruction stream may be
+	  corrupted when dynamic high-level clock gating is enabled.
+	  This workaround disables gating the Core clock when the Instruction
+	  side is waiting for a Page Table Walk answer or linefill completion.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 787c06ada555..d62847df3df5 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -54,6 +54,7 @@
 #define L2X0_LINE_TAG			0xF30
 #define L2X0_DEBUG_CTRL			0xF40
 #define L2X0_PREFETCH_OFFSET		0xF60
+#define L2X0_PWR_CTRL			0xF80
 
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d09ff3b13b54..15f09825df2b 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -100,6 +100,7 @@ void __init tegra_init_cache(void)
 	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
 	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
 	writel(7, p + L2X0_PREFETCH_OFFSET);
+	writel(2, p + L2X0_PWR_CTRL);
 
 	l2x0_init(p, 0x7C480001, 0x8200c3fe);
 #endif
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index 91d787f2adcb..1ca815d0fab8 100644
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -536,6 +536,8 @@ ENTRY(__cortex_a9_l2x0_restart)
 	str	r6, [r9, #L2X0_DATA_LATENCY_CTRL]
 	str	r7, [r9, #L2X0_PREFETCH_OFFSET]
 	str	r4, [r9, #L2X0_AUX_CTRL]
+	mov     r4, #0x2                @ L2X0_DYNAMIC_CLK_GATING_EN
+	str     r4, [r9, #L2X0_PWR_CTRL]
 	cmp	r0, #0
 
 	beq	__reenable_l2x0
diff --git a/arch/arm/mach-tegra/kfuse.c b/arch/arm/mach-tegra/kfuse.c
index b2439f5a4ae2..f5de828bb508 100644
--- a/arch/arm/mach-tegra/kfuse.c
+++ b/arch/arm/mach-tegra/kfuse.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/string.h>
+#include <linux/delay.h>
 
 #include <mach/iomap.h>
 #include <mach/kfuse.h>
@@ -46,13 +47,17 @@ static inline void tegra_kfuse_writel(u32 value, unsigned long offset)
 	tegra_apb_writel(value, TEGRA_KFUSE_BASE + offset);
 }
 
-static void wait_for_done(void)
+static int wait_for_done(void)
 {
 	u32 reg;
-
+	int retries = 50;
 	do {
 		reg = tegra_kfuse_readl(KFUSE_STATE);
-	} while ((reg & KFUSE_STATE_DONE) == 0);
+		if (reg & KFUSE_STATE_DONE);
+			return 0;
+		msleep(10);
+	} while(--retries);
+	return -ETIMEDOUT;
 }
 
 /* read up to KFUSE_DATA_SZ bytes into dest.
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8cdf3bf26719..de77d5b4271a 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -238,6 +238,16 @@ __v7_setup:
 2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
 	teq	r0, r10
 	bne	3f
+	cmp	r6, #0x10			@ power ctrl reg added r1p0
+	mrcge	p15, 0, r10, c15, c0, 0		@ read power control register
+	orrge	r10, r10, #1			@ enable dynamic clock gating
+	mcrge	p15, 0, r10, c15, c0, 0		@ write power control register
+#ifdef CONFIG_ARM_ERRATA_720791
+	teq	r5, #0x00100000			@ only present in r1p*
+	mrceq	p15, 0, r10, c15, c0, 2		@ read "chicken power ctrl" reg
+	orreq	r10, r10, #0x30			@ disable core clk gate on
+	mcreq	p15, 0, r10, c15, c0, 2		@ instr-side waits
+#endif
 #ifdef CONFIG_ARM_ERRATA_742230
 	cmp	r6, #0x22			@ only present up to r2p2
 	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register