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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 09:00:40 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 09:00:40 -0700
commit1d767cae4dbd4116fc3b2cc3251a20760f98339f (patch)
tree79a1a48a67a9b4296ce062d61ee863fe7a46c77f /arch/sh/mm/tlb-sh5.c
parent6101167727932a929e37fb8a6eeb68bdbf54d58e (diff)
parent5f19f14fed7786652b9617c633db101d26a42251 (diff)
Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt: - New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A) - New boards: RSK2+SH7264, RSK2+SH7269 - Unbreaking kgdb for SMP - Consolidation of _32/_64 page fault handling. - watchdog and legacy DMA chainsawing, part 1 - Conversion to evt2irq() hwirq lookup, to support relocation of vectored IRQs for irqdomains. * tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (98 commits) sh: intc: Kill off special reservation interface. sh: Enable PIO API for hp6xx and se770x. sh: Kill off machvec IRQ hinting. sh: dma: More legacy cpu dma chainsawing. sh: Kill off MAX_DMA_ADDRESS leftovers. sh: Tidy up some of the cpu legacy dma header mess. sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a. sh64: Fix up vmalloc fault range check. Revert "sh: Ensure fixmap and store queue space can co-exist." serial: sh-sci: Fix for port types without BRI interrupts. sh: legacy PCI evt2irq migration. sh: cpu dma evt2irq migration. sh: sh7763rdp evt2irq migration. sh: sdk7780 evt2irq migration. sh: migor evt2irq migration. sh: landisk evt2irq migration. sh: kfr2r09 evt2irq migration. sh: ecovec24 evt2irq migration. sh: ap325rxa evt2irq migration. sh: urquell evt2irq migration. ...
Diffstat (limited to 'arch/sh/mm/tlb-sh5.c')
-rw-r--r--arch/sh/mm/tlb-sh5.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index f27dbe1c1599..3aea25dc431a 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -182,3 +182,43 @@ void tlb_unwire_entry(void)
local_irq_restore(flags);
}
+
+void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+{
+ unsigned long long ptel;
+ unsigned long long pteh=0;
+ struct tlb_info *tlbp;
+ unsigned long long next;
+ unsigned int fault_code = get_thread_fault_code();
+
+ /* Get PTEL first */
+ ptel = pte.pte_low;
+
+ /*
+ * Set PTEH register
+ */
+ pteh = neff_sign_extend(address & MMU_VPN_MASK);
+
+ /* Set the ASID. */
+ pteh |= get_asid() << PTEH_ASID_SHIFT;
+ pteh |= PTEH_VALID;
+
+ /* Set PTEL register, set_pte has performed the sign extension */
+ ptel &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
+
+ if (fault_code & FAULT_CODE_ITLB)
+ tlbp = &cpu_data->itlb;
+ else
+ tlbp = &cpu_data->dtlb;
+
+ next = tlbp->next;
+ __flush_tlb_slot(next);
+ asm volatile ("putcfg %0,1,%2\n\n\t"
+ "putcfg %0,0,%1\n"
+ : : "r" (next), "r" (pteh), "r" (ptel) );
+
+ next += TLB_STEP;
+ if (next > tlbp->last)
+ next = tlbp->first;
+ tlbp->next = next;
+}