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authorMarkos Chandras <markos.chandras@imgtec.com>2014-07-14 12:43:28 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-08-02 00:06:38 +0200
commite647e6b5b355bbf58d5c20c181e69474e5aee5fe (patch)
tree7ee083801d1ca02986bcb972602a8b4428aea964 /arch/mips/include/asm/cpu.h
parent03a58777de0895864ccdb93249f3ce8d9fcc13ac (diff)
MIPS: cpu: Add new cpu option for Hardware Table Walker.
Moreover, report hardware page table walker support as 'htw' in the ASE list of /proc/cpuinfo, if the core implements this feature. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
-rw-r--r--arch/mips/include/asm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index abacaa1f7293..ec6a0f964d6a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -365,6 +365,7 @@ enum cpu_type_enum {
#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
+#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
/*
* CPU ASE encodings