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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2014-09-25 23:38:25 +0200
committerStefan Agner <stefan.agner@toradex.com>2014-10-28 14:42:55 +0100
commit0625688b466897845df130df7d66cb9ce8c369bb (patch)
treef74f5b15d8cd91d3e59ce8932ded92ffaaeb8d17 /arch/arm
parentd53e5314cb04786b7cab4afe5529a06fbf5f7db8 (diff)
apalis/colibri t30: fix audio hub lock-up
This patch fixes a clock related audio hub driver lock-up observed when booting with mainline U-Boot which we are in the process of migrating to now.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/board-apalis_t30.c4
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30.c9
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c
index a3e1ad6b1ade..8b05b824b390 100644
--- a/arch/arm/mach-tegra/board-apalis_t30.c
+++ b/arch/arm/mach-tegra/board-apalis_t30.c
@@ -324,9 +324,12 @@ static void __init apalis_t30_mcp2515_can_init(void)
/* Clocks */
static struct tegra_clk_init_table apalis_t30_clk_init_table[] __initdata = {
/* name parent rate enabled */
+ {"apbif", "clk_m", 12000000, false},
+ {"audio0", "i2s0_sync", 0, false},
{"audio1", "i2s1_sync", 0, false},
{"audio2", "i2s2_sync", 0, false},
{"audio3", "i2s3_sync", 0, false},
+ {"audio4", "i2s4_sync", 0, false},
{"blink", "clk_32k", 32768, true},
/* required for vi_sensor ? */
{"csus", "clk_m", 0, true},
@@ -345,6 +348,7 @@ static struct tegra_clk_init_table apalis_t30_clk_init_table[] __initdata = {
{"i2s1", "pll_a_out0", 0, false},
{"i2s2", "pll_a_out0", 0, false},
{"i2s3", "pll_a_out0", 0, false},
+ {"i2s4", "pll_a_out0", 0, false},
{"pll_a", NULL, 564480000, true},
{"pll_m", NULL, 0, false},
{"pwm", "pll_p", 3187500, false},
diff --git a/arch/arm/mach-tegra/board-colibri_t30.c b/arch/arm/mach-tegra/board-colibri_t30.c
index 8afffe4b48d6..f449ac0d057e 100644
--- a/arch/arm/mach-tegra/board-colibri_t30.c
+++ b/arch/arm/mach-tegra/board-colibri_t30.c
@@ -329,17 +329,20 @@ static struct platform_device colibri_can_device = {
/* Clocks */
static struct tegra_clk_init_table colibri_t30_clk_init_table[] __initdata = {
/* name parent rate enabled */
+ {"apbif", "clk_m", 12000000, false},
+ {"audio0", "i2s0_sync", 0, false},
{"audio1", "i2s1_sync", 0, false},
{"audio2", "i2s2_sync", 0, false},
{"audio3", "i2s3_sync", 0, false},
+ {"audio4", "i2s4_sync", 0, false},
{"blink", "clk_32k", 32768, true},
/* optional camera clock */
- { "clk_out_2", "extern2", 24000000, false},
+ {"clk_out_2", "extern2", 24000000, false},
{"d_audio", "clk_m", 12000000, false},
{"dam0", "clk_m", 12000000, false},
{"dam1", "clk_m", 12000000, false},
{"dam2", "clk_m", 12000000, false},
- { "extern2", "clk_m", 24000000, false},
+ {"extern2", "clk_m", 24000000, false},
{"hda", "pll_p", 108000000, false},
{"hda2codec_2x","pll_p", 48000000, false},
{"i2c1", "pll_p", 3200000, false},
@@ -351,10 +354,12 @@ static struct tegra_clk_init_table colibri_t30_clk_init_table[] __initdata = {
{"i2s1", "pll_a_out0", 0, false},
{"i2s2", "pll_a_out0", 0, false},
{"i2s3", "pll_a_out0", 0, false},
+ {"i2s4", "pll_a_out0", 0, false},
{"nor", "pll_p", 86500000, true},
{"pll_a", NULL, 564480000, true},
{"pll_m", NULL, 0, false},
{"pwm", "pll_p", 3187500, false},
+ {"spdif_out", "pll_a_out0", 0, false},
{"vi", "pll_p", 0, false},
{NULL, NULL, 0, 0},
};