diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-05-22 17:45:45 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 35e90b28412635790274a7ea476d4bb3dbcda065 (patch) | |
| tree | 2b96375d157e17c217eaa90d99d164357f29e5d8 /arch/arm64 | |
| parent | edac894a8b03f2c3235d1f3d363cf1a064d45b43 (diff) | |
MLK-18386 ARM64: dts: imx8mm: fix pcie pll can't be locked in resume
pcie aux clock is mandatory required by pcie power management.
add the aux clock into imx8mm pcie dts node explicitly.
pcie ctrl clock would be turned on, when pcie root clock
is enabled.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index cb2bef49d03a..59bd5a61968b 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -939,7 +939,7 @@ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, - <&clk IMX8MM_CLK_PCIE1_CTRL_CG>, + <&clk IMX8MM_CLK_PCIE1_AUX_CG>, <&clk IMX8MM_CLK_PCIE1_PHY_CG>; clock-names = "pcie", "pcie_bus", "pcie_phy"; fsl,max-link-speed = <2>; |