diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-06-12 15:27:06 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 287a5923bcc83ed3cdf2592cfa1e8f0a80ef7a8d (patch) | |
| tree | 8740f7652e10012332edc22d27576fc9de094c41 /arch/arm64 | |
| parent | 243663c72d269ceb438f312e5fcc5bcb02e110e0 (diff) | |
MLK-18576-2 arm64: fsl-imx8dx.dtsi: Add aux props for LDB nodes
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds DT properties in the LDB nodes
so that HWs needed by dual channel mode can be supplied.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 05fa8921e68c..df2d716dd363 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1790,18 +1790,21 @@ #size-cells = <0>; compatible = "fsl,imx8qxp-ldb"; clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, - <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; - clock-names = "pixel", "bypass"; - power-domains = <&pd_mipi_dsi_0_lvds>; + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_0_lvds>, <&pd_mipi_dsi_1_lvds>; gpr = <&lvds_region1>; + aux-gpr = <&lvds_region2>; status = "disabled"; lvds-channel@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - phys = <&ldb1_phy>; - phy-names = "ldb_phy"; + phys = <&ldb1_phy>, <&ldb2_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; status = "disabled"; port@0 { @@ -1951,18 +1954,21 @@ #size-cells = <0>; compatible = "fsl,imx8qxp-ldb"; clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, - <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; - clock-names = "pixel", "bypass"; - power-domains = <&pd_mipi_dsi_1_lvds>; + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_1_lvds>, <&pd_mipi_dsi_0_lvds>; gpr = <&lvds_region2>; + aux-gpr = <&lvds_region1>; status = "disabled"; lvds-channel@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - phys = <&ldb2_phy>; - phy-names = "ldb_phy"; + phys = <&ldb2_phy>, <&ldb1_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; status = "disabled"; port@0 { |