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authorMarek Szyprowski <m.szyprowski@samsung.com>2011-08-13 12:55:36 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-08-19 20:57:38 +0900
commit3f6065dd9d2c947c8d68336f07bd721d3909a30d (patch)
tree248a3ccfa6f785cc08f1c4cf5ab9fcc891f0c125 /arch/arm/plat-s5p
parent70b0e82bc7d03d33de5bceea92d419a9be4340ee (diff)
ARM: S5P: add required chained_irq_enter/exit to gpio-int code
This patch adds chained IRQ enter/exit functions to gpio interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 327ab9f662e8..f71078ef6bb5 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -23,6 +23,8 @@
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
+#include <asm/mach/irq.h>
+
#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
#define CON_OFFSET 0x700
@@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
int group, pend_offset, mask_offset;
unsigned int pend, mask;
+ struct irq_chip *chip = irq_get_chip(irq);
+ chained_irq_enter(chip, desc);
+
for (group = 0; group < bank->nr_groups; group++) {
struct s3c_gpio_chip *chip = bank->chips[group];
if (!chip)
@@ -102,6 +107,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
pend &= ~BIT(offset);
}
}
+ chained_irq_exit(chip, desc);
}
static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)