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authorWill Deacon <will.deacon@arm.com>2011-02-28 18:15:16 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-09 21:40:12 +0000
commitfcbdc5fe6ebe07d502c9b652cb63376bcc4227ac (patch)
tree6472c243e21776c0fcac35d01b77924ed1c16e11 /arch/arm/mm
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
On the r2p* and r3p* versions of the Cortex-A9, a speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-v7.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8e3356239136..f7498f1a2e86 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,10 +108,16 @@ ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_ARM_ERRATA_430973
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif
+#ifdef CONFIG_ARM_ERRATA_754322
+ dsb
+#endif
mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
isb
1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
isb
+#ifdef CONFIG_ARM_ERRATA_754322
+ dsb
+#endif
mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb
#endif