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| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-04-18 17:12:14 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-04-18 17:12:14 +0100 |
| commit | fac56c2df51bc29b07b3c2dcfabf32a015a0522c (patch) | |
| tree | 1ff5d84ecf4ea0bcbd42e2ef9624b5ade3810890 /arch/arm/mm/cache-v7.S | |
| parent | 6caa15d0b84d2ea688fd31f4f172c8353463e109 (diff) | |
| parent | a6360dd37e1a144ed11e6548371bade559a1e4df (diff) | |
Merge commit 'v2.6.39-rc3' into for-2.6.39
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce953..dc18d81ef8ce 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * |