diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-07-25 13:24:13 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:27:17 -0700 |
| commit | 8583997652ef54ca4c41c3271ad49147bdee9340 (patch) | |
| tree | 83918da528ad0cc895542fc8918fb0d4b6244908 /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 7aff2dbfa40347abb84a7517bf95953f73e372de (diff) | |
ARM: tegra: power: Add LP2 in idle support for secondary CPUs
Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 9a089a605378..abaea8b868f1 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -136,6 +136,22 @@ ENTRY(tegra3_sleep_cpu) ENDPROC(tegra3_sleep_cpu) /* + * tegra3_sleep_cpu_secondary(unsigned long v2p) + * + * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. + */ +ENTRY(tegra3_sleep_cpu_secondary) + mov r3, lr @ set resume address to lr + bl tegra_cpu_save + bl tegra_cpu_exit_coherency + + /* Powergate this CPU. */ + mov r0, #0 @ power mode flags (!hotplug) + bl tegra3_cpu_reset + b . @ should never get here +ENDPROC(tegra3_sleep_cpu_secondary) + +/* * tegra3_tear_down_cpu * * Switches the CPU cluster to PLL-P and enters sleep. |