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authorNikesh Oswal <noswal@nvidia.com>2011-01-24 16:40:29 +0530
committerNiket Sirsi <nsirsi@nvidia.com>2011-01-25 15:26:55 -0800
commit4c583e3e70d08f78c7b0c0bb56d6b7115e7339fe (patch)
treece04d79c23e7774d9b7456fe6b82daaaeb678eaa /arch/arm/mach-tegra/board-whistler.c
parentc2aece97469747851ab911591b549721a37c194f (diff)
[ARM] tegra: whistler: added members to i2s data
Added more members to i2s platform data. These members will be used by i2s driver to set i2s controller. Change-Id: I32d7d49122a15e8a8500b65c4f15a10b6c01b3d8 Reviewed-on: http://git-master/r/16704 Tested-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-whistler.c')
-rw-r--r--arch/arm/mach-tegra/board-whistler.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c
index e05811168569..bacc939c5057 100644
--- a/arch/arm/mach-tegra/board-whistler.c
+++ b/arch/arm/mach-tegra/board-whistler.c
@@ -291,26 +291,39 @@ static void whistler_i2c_init(void)
platform_device_register(&tegra_i2c_device1);
}
+
static struct tegra_audio_platform_data tegra_audio_pdata[] = {
/* For I2S1 */
[0] = {
+ .i2s_master = true,
+ .dsp_master = false,
.dma_on = true, /* use dma by default */
+ .i2s_master_clk = 44100,
+ .dsp_master_clk = 8000,
.i2s_clk_rate = 240000000,
.dap_clk = "clk_dev1",
.audio_sync_clk = "audio_2x",
.mode = I2S_BIT_FORMAT_I2S,
- .fifo_fmt = I2S_FIFO_16_LSB,
+ .fifo_fmt = I2S_FIFO_PACKED,
.bit_size = I2S_BIT_SIZE_16,
+ .i2s_bus_width = 32,
+ .dsp_bus_width = 16,
},
/* For I2S2 */
[1] = {
+ .i2s_master = false,
+ .dsp_master = true,
.dma_on = true, /* use dma by default */
+ .i2s_master_clk = 44100,
+ .dsp_master_clk = 8000,
.i2s_clk_rate = 240000000,
.dap_clk = "clk_dev1",
.audio_sync_clk = "audio_2x",
- .mode = I2S_BIT_FORMAT_I2S,
+ .mode = I2S_BIT_FORMAT_DSP,
.fifo_fmt = I2S_FIFO_16_LSB,
.bit_size = I2S_BIT_SIZE_16,
+ .i2s_bus_width = 32,
+ .dsp_bus_width = 16,
}
};