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| author | Pradeep Goudagunta <pgoudagunta@nvidia.com> | 2010-12-17 16:15:05 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:49:02 -0700 |
| commit | 252214ee4c4d3fea96fb2ca53e3f601a70f6c3a1 (patch) | |
| tree | 19a8ed76054f22ed7f2db6664512abf49e83effe /arch/arm/mach-tegra/board-aruba.c | |
| parent | 3e954cc82f424fc6700be1d62259ec910265162d (diff) | |
[ARM] tegra:uart:Reseting Tx fifo in non fifo mode
If Tx fifo is reset in fifo mode then extra bytes were seen in receiver end
ASIC team recommended following as SW workaround
-Disable fifo mode
-Delay for 8x clock cycles
-Reset Tx fifo
-Enable fifo mode
Bug : 742346
Original-Change-Id: Ia091d0050dd7137e874acc2948e517b76c0743b6
Reviewed-on: http://git-master/r/13610
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Iebc31029adbe2b4d5d56403d09cf5636a5160262
Diffstat (limited to 'arch/arm/mach-tegra/board-aruba.c')
0 files changed, 0 insertions, 0 deletions