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authorAnand Gadiyar <gadiyar@ti.com>2010-07-14 13:38:49 +0000
committerTony Lindgren <tony@atomide.com>2010-08-04 14:43:52 +0300
commit58dcfb3a0f5eb0a882f7b696d4d2dc49b709ce5c (patch)
treeb7595934e1d30cdc7a0c5b3b39109ebe464ada85 /arch/arm/mach-omap2
parentb0a1a6ce0597662c06f970643da60b8ebb5cdd1c (diff)
omap: 3630: disable TLL SAR on 3630 ES1
USBTLL Save-and-Restore is broken in 3630 ES1.0. Having it enabled could result in incorrect register restores as the OMAP exits off-mode. This could potentially result in unexpected wakeup events. (Refer 3630 errata ID i579) This is fixed in ES1.1. So disable it for ES1.0s. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index bd87112beea8..fa904861668b 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = {
},
};
+/*
+ * The USBTLL Save-and-Restore mechanism is broken on
+ * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
+ * needs to be disabled on these chips.
+ * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
CHIP_IS_OMAP3430ES2 |
- CHIP_IS_OMAP3430ES3_0),
+ CHIP_IS_OMAP3430ES3_0 |
+ CHIP_IS_OMAP3630ES1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
@@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
static struct powerdomain core_3xxx_es3_1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
- .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
+ CHIP_GE_OMAP3630ES1_1),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */