diff options
author | Roshni Shah <shah.roshni@yahoo.com> | 2011-03-14 06:49:42 -0400 |
---|---|---|
committer | Justin Waters <justin.waters@timesys.com> | 2012-03-02 16:59:46 -0500 |
commit | 2731b2eadeaa141e6f305fa8086106608112bbaa (patch) | |
tree | 2702d45bac84073cd580ccb1bd3eafb9a000d3b6 /arch/arm/mach-mx28 | |
parent | 6d23f5084c975be637f7d748db82116bf84d3872 (diff) |
Add support for the i.MX53 QSB2.6.35.3-mx53-early-201103141049
This patch seems to have originated from the 11.01.00 release
from Freescale, which is no longer available except through the
gitweb interface from Freescale.
http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=commit;h=27fdf7bae11978d21e8aba09bb635f49b07edd4a
Diffstat (limited to 'arch/arm/mach-mx28')
44 files changed, 23111 insertions, 0 deletions
diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig new file mode 100644 index 000000000000..dc1d8b115869 --- /dev/null +++ b/arch/arm/mach-mx28/Kconfig @@ -0,0 +1,25 @@ +choice + prompt "Select i.MXS board type" + +config MACH_MX28EVK + bool "Freescale MX28 EVK board" + depends on ARCH_MX28 + select USB_ARCH_HAS_EHCI + +endchoice + +config VECTORS_PHY_ADDR + int "vectors address" + default 0 + help + This config set vectors table is located which physical address + +config MXS_TIMER_WITH_MACH + bool "System Timer support Compare Match interrupt" + default y + +config MEM_mDDR + bool "Memory type is mDDR" + depends on ARCH_MX28 + help + Say Y to select mDDR memory diff --git a/arch/arm/mach-mx28/Makefile b/arch/arm/mach-mx28/Makefile new file mode 100644 index 000000000000..23869ad9cbbc --- /dev/null +++ b/arch/arm/mach-mx28/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# +obj-y += pinctrl.o clock.o device.o serial.o power.o bus_freq.o pm.o sleep.o + +# Board select +obj-$(CONFIG_MACH_MX28EVK) += mx28evk.o mx28evk_pins.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_MXS_RAM_FREQ_SCALING) +=emi.o emi_settings.o + +# USB support +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o diff --git a/arch/arm/mach-mx28/Makefile.boot b/arch/arm/mach-mx28/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-mx28/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c new file mode 100644 index 000000000000..920c6309e886 --- /dev/null +++ b/arch/arm/mach-mx28/bus_freq.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module. + * + * @ingroup PM + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/notifier.h> +#include <linux/cpufreq.h> + +#include <mach/hardware.h> +#include <linux/io.h> +#include <asm/system.h> +#include <mach/clock.h> +#include <mach/bus_freq.h> + +#include "regs-clkctrl.h" +#include "regs-digctl.h" + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#ifdef CONFIG_MEM_mDDR +struct profile profiles[] = { + { 454736, 151570, 205710, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 360000, 120000, 130910, 0, 1350000, + 1250000, 200000, 3300000, 1750000, 24000, 0 }, + { 261818, 130910, 130910, 0, 1350000, + 1250000, 173000, 3300000, 1750000, 24000, 0 }, + { 64000, 64000, 240000, 3, 1350000, + 1250000, 150000, 3300000, 1750000, 24000, 0 }, + { 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 }, +}; +#else +struct profile profiles[] = { + { 454736, 151570, 205710, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 360000, 120000, 130910, 0, 1350000, + 1250000, 200000, 3300000, 1750000, 24000, 0 }, + { 261818, 130910, 130910, 0, 1350000, + 1250000, 173000, 3300000, 1750000, 24000, 0 }, + { 64000, 64000, 130910, 3, 1350000, + 1250000, 150000, 3300000, 1750000, 24000, 0 }, + { 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 }, +}; +#endif +static struct device *busfreq_dev; +static struct clk *usb_clk0; +static struct clk *usb_clk1; +static struct clk *lcdif_clk; +u32 clkseq_setting; + +int low_freq_used(void) +{ + if ((clk_get_usecount(usb_clk0) == 0) + && (clk_get_usecount(usb_clk1) == 0) + && (clk_get_usecount(lcdif_clk) == 0)) + return 1; + else + return 0; +} + +int is_hclk_autoslow_ok(void) +{ + if ((clk_get_usecount(usb_clk0) == 0) + && (clk_get_usecount(usb_clk1) == 0)) + return 1; + else + return 0; +} + +int timing_ctrl_rams(int ss) +{ + __raw_writel(BF(ss, DIGCTL_ARMCACHE_VALID_SS) | + BF(ss, DIGCTL_ARMCACHE_DRTY_SS) | + BF(ss, DIGCTL_ARMCACHE_CACHE_SS) | + BF(ss, DIGCTL_ARMCACHE_DTAG_SS) | + BF(ss, DIGCTL_ARMCACHE_ITAG_SS), + DIGCTRL_BASE_ADDR + HW_DIGCTL_ARMCACHE); + return 0; +} + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + int ret = 0; + + busfreq_dev = &pdev->dev; + + usb_clk0 = clk_get(NULL, "usb_clk0"); + if (IS_ERR(usb_clk0)) { + ret = PTR_ERR(usb_clk0); + goto out_usb0; + } + + usb_clk1 = clk_get(NULL, "usb_clk1"); + if (IS_ERR(usb_clk1)) { + ret = PTR_ERR(usb_clk1); + goto out_usb1; + } + + lcdif_clk = clk_get(NULL, "dis_lcdif"); + if (IS_ERR(lcdif_clk)) { + ret = PTR_ERR(lcdif_clk); + goto out_lcd; + } + return 0; + +out_lcd: + clk_put(usb_clk1); +out_usb1: + clk_put(usb_clk0); +out_usb0: + return ret; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "busfreq", + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c new file mode 100644 index 000000000000..9797d1f650d9 --- /dev/null +++ b/arch/arm/mach-mx28/clock.c @@ -0,0 +1,1818 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/iram_alloc.h> +#include <linux/platform_device.h> + +#include <mach/clock.h> + +#include "regs-clkctrl.h" +#include "regs-digctl.h" +#include "emi_settings.h" + +#define HW_SAIF_CTRL (0x00000000) +#define HW_SAIF_STAT (0x00000010) +#define SAIF0_CTRL (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF0_STAT (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_STAT) +#define SAIF1_CTRL (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF1_STAT (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_STAT) +#define BM_SAIF_CTRL_RUN 0x00000001 +#define BM_SAIF_STAT_BUSY 0x00000001 +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) + +/* external clock input */ +static struct clk xtal_clk[]; +static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; + +static unsigned long enet_mii_phy_rate; + +static inline int clk_is_busy(struct clk *clk) +{ + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); +} + +static bool mx28_enable_h_autoslow(bool enable) +{ + bool currently_enabled; + + if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_ASM_ENABLE) + currently_enabled = true; + else + currently_enabled = false; + + if (enable) + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + else + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + return currently_enabled; +} + + +static void mx28_set_hbus_autoslow_flags(u16 mask) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= 0xFFFF; + reg |= mask << 16; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); +} + +static int mx28_raw_enable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } + return 0; +} + +static void mx28_raw_disable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } +} + +static unsigned int +mx28_get_frac_div(unsigned long root_rate, unsigned long rate, unsigned mask) +{ + unsigned long mult_rate; + unsigned int div; + mult_rate = rate * (mask + 1); + div = mult_rate / root_rate; + if ((mult_rate % root_rate) && (div < mask)) + div--; + return div; +} + +static unsigned long xtal_get_rate(struct clk *clk) +{ + int id = clk - xtal_clk; + return xtal_clk_rate[id]; +} + +static struct clk xtal_clk[] = { + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, +}; + +static struct clk ref_xtal_clk = { + .parent = &xtal_clk[0], +}; + +static unsigned long pll_get_rate(struct clk *clk); +static int pll_enable(struct clk *clk); +static void pll_disable(struct clk *clk); +static int pll_set_rate(struct clk *clk, unsigned long rate); +static struct clk pll_clk[] = { + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + } +}; + +static unsigned long pll_get_rate(struct clk *clk) +{ + unsigned int reg; + if (clk == (pll_clk + 2)) + return 50000000; + if (clk == pll_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + reg = (reg & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) >> + BP_CLKCTRL_PLL0CTRL0_DIV_SEL; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + reg = (reg & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) >> + BP_CLKCTRL_PLL1CTRL0_DIV_SEL; + } + switch (reg) { + case 0: + return 480000000; + case 1: + return 384000000; + case 2: + return 288000000; + default: + return -EINVAL; + } +} + +static int pll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div, reg; + + if (clk == pll_clk + 2) + return -EINVAL; + + switch (rate) { + case 480000000: + div = 0; + break; + case 384000000: + div = 1; + break; + case 288000000: + div = 2; + break; + default: + return -EINVAL; + } + if (clk == pll_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + reg &= ~BM_CLKCTRL_PLL0CTRL0_DIV_SEL; + reg |= BF_CLKCTRL_PLL0CTRL0_DIV_SEL(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + reg &= ~BM_CLKCTRL_PLL1CTRL0_DIV_SEL; + reg |= BF_CLKCTRL_PLL1CTRL0_DIV_SEL(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + } + return 0; +} + +static int pll_enable(struct clk *clk) +{ + int timeout = 100; + unsigned long reg; + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL0CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL0CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL1CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL1CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + udelay(10); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return -ENODEV; +} + +static void pll_disable(struct clk *clk) +{ + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_CLR); + return; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_CLR); + return; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return; +} + +static inline unsigned long +ref_clk_get_rate(unsigned long base, unsigned int div) +{ + unsigned long rate = base / 1000; + return 1000 * ((rate * 18) / div); +} + +static unsigned long ref_clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = (base * 18) / rate; + return (base / div) * 18; +} + +static int ref_clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = ((base/1000) * 18) / (rate/1000); + if (rate != ((base / div) * 18)) + return -EINVAL; + if (clk->scale_reg == 0) + return -EINVAL; + base = __raw_readl(clk->scale_reg); + base &= ~(0x3F << clk->scale_bits); + base |= (div << clk->scale_bits); + __raw_writel(base, clk->scale_reg); + return 0; +} + +static unsigned long ref_cpu_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_CPUFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + + +static struct clk ref_cpu_clk = { + .parent = &pll_clk[0], + .get_rate = ref_cpu_get_rate, + .round_rate = ref_clk_round_rate, + .set_rate = ref_clk_set_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATECPU, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_CPUFRAC, +}; + +static unsigned long ref_emi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_EMIFRAC; + reg >>= BP_CLKCTRL_FRAC0_EMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_emi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_emi_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEEMI, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_EMIFRAC, +}; + +static unsigned long ref_io_get_rate(struct clk *clk); +static struct clk ref_io_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO0, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_IO0FRAC, + }, + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO1, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_IO1FRAC, + }, +}; + +static unsigned long ref_io_get_rate(struct clk *clk) +{ + unsigned int reg; + if (clk == ref_io_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO0FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO0FRAC; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO1FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO1FRAC; + } + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static unsigned long ref_pix_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_PIXFRAC; + reg >>= BP_CLKCTRL_FRAC1_PIXFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_pix_clk = { + .parent = &pll_clk[0], + .get_rate = ref_pix_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEPIX, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_PIXFRAC, +}; + +static unsigned long ref_hsadc_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_HSADCFRAC; + reg >>= BP_CLKCTRL_FRAC1_HSADCFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_hsadc_clk = { + .parent = &pll_clk[0], + .get_rate = ref_hsadc_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEHSADC, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_HSADCFRAC, +}; + +static unsigned long ref_gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_GPMIFRAC; + reg >>= BP_CLKCTRL_FRAC1_GPMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_gpmi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_gpmi_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEGPMI, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_GPMIFRAC, +}; + +static unsigned long cpu_get_rate(struct clk *clk) +{ + unsigned long rate, div; + rate = (clk->parent->get_rate(clk->parent)); + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU) & + BM_CLKCTRL_CPU_DIV_CPU; + rate = rate/div; + return rate; + } + +static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long frac_rate, root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_cpu_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static struct clk h_clk; +static int cpu_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = + clk->parent->parent->get_rate(clk->parent->parent); + int i; + u32 clkctrl_cpu = 1; + u32 c = clkctrl_cpu; + u32 clkctrl_frac = 1; + u32 val; + u32 reg_val, hclk_reg; + + if (rate < 24000) + return -EINVAL; + else if (rate == 24000) { + /* switch to the 24M source */ + clk_set_parent(clk, &ref_xtal_clk); + } else { + for ( ; c < 0x40; c++) { + u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) / + (rate/1000); + int s1, s2; + + if (f < 18 || f > 35) + continue; + s1 = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + s2 = (root_rate/1000)*18/c/f - (rate/1000); + if (abs(s1) > abs(s2)) { + clkctrl_cpu = c; + clkctrl_frac = f; + } + if (s2 == 0) + break; + }; + if (c == 0x40) { + int d = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + if ((abs(d) > 100) || (clkctrl_frac < 18) || + (clkctrl_frac > 35)) + return -EINVAL; + } + + /* Set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpuclk is sufficiently + * high for the hbus clock. + */ + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + if ((hclk_reg & BP_CLKCTRL_HBUS_DIV) != 3) { + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= BF_CLKCTRL_HBUS_DIV(3); + + /* change hclk divider to safe value for any ref_cpu + * value. + */ + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_HBUS); + } + + for (i = 10000; i; i--) + if (!clk_is_busy(&h_clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up HCLK divisor\n"); + return -ETIMEDOUT; + } + + /* Set Frac div */ + val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + val &= ~(BM_CLKCTRL_FRAC0_CPUFRAC << BP_CLKCTRL_FRAC0_CPUFRAC); + val |= clkctrl_frac; + __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + /* Do not gate */ + __raw_writel(BM_CLKCTRL_FRAC0_CLKGATECPU, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_FRAC0_CLR); + + /* write clkctrl_cpu */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + reg_val &= ~0x3F; + reg_val |= clkctrl_cpu; + + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up CPU divisor\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static int cpu_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_cpu_clk)) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static struct clk cpu_clk = { + .parent = &ref_cpu_clk, + .get_rate = cpu_get_rate, + .round_rate = cpu_round_rate, + .set_rate = cpu_set_rate, + .set_parent = cpu_set_parent, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 18, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .busy_bits = 28, +}; + +static unsigned long uart_get_rate(struct clk *clk) +{ + unsigned int div; + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) & + BM_CLKCTRL_XTAL_DIV_UART; + return clk->parent->get_rate(clk->parent) / div; +} + +static struct clk uart_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE, + .get_rate = uart_get_rate, +}; + +static struct clk pwm_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE, +}; + +static unsigned long clk_32k_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static struct clk clk_32k = { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE, + .get_rate = clk_32k_get_rate, +}; + +static unsigned long lradc_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 16; +} + +static struct clk lradc_clk = { + .parent = &clk_32k, + .flags = RATE_FIXED, + .get_rate = lradc_get_rate, +}; + +static unsigned long x_get_rate(struct clk *clk) +{ + unsigned long reg, div; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + div = reg & BM_CLKCTRL_XBUS_DIV; + if (!(reg & BM_CLKCTRL_XBUS_DIV_FRAC_EN)) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x400) * div; +} + +static unsigned long x_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static int x_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return -EINVAL; + + if (root_rate % rate) { + div = mx28_get_frac_div(root_rate / 1000, rate / 1000, 0x3FF); + if (((root_rate / 0x400) * div) > rate) + return -EINVAL; + } + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~(BM_CLKCTRL_XBUS_DIV | BM_CLKCTRL_XBUS_DIV_FRAC_EN); + if (root_rate % rate) + reg |= BM_CLKCTRL_XBUS_DIV_FRAC_EN; + reg |= BF_CLKCTRL_XBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + return 0; +} + +static struct clk x_clk = { + .parent = &ref_xtal_clk, + .get_rate = x_get_rate, + .set_rate = x_set_rate, + .round_rate = x_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .scale_bits = BM_CLKCTRL_XBUS_BUSY, +}; + +static struct clk ana_clk = { + .parent = &ref_xtal_clk, +}; + +static unsigned long rtc_get_rate(struct clk *clk) +{ + if (clk->parent == &xtal_clk[2]) + return clk->parent->get_rate(clk->parent); + return clk->parent->get_rate(clk->parent) / 768; +} + +static struct clk rtc_clk = { + .parent = &ref_xtal_clk, + .get_rate = rtc_get_rate, +}; + +static struct clk flexcan_clk[] = { + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN0, + }, + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN1, + }, +}; + +static unsigned long h_get_rate(struct clk *clk) +{ + unsigned long reg, div; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + div = reg & BM_CLKCTRL_HBUS_DIV; + return clk->parent->get_rate(clk->parent) / div; +} + +static unsigned long h_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x20)) + return root_rate; + if (frac_rate < (rate / 2)) + return rate; + else + return root_rate / (div + 1); +} + +static int h_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned long round_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + round_rate = h_round_rate(clk, rate); + div = root_rate / round_rate; + if ((div == 0) || (div >= 0x20)) + return -EINVAL; + + if (root_rate % round_rate) + return -EINVAL; + + if ((root_rate < rate) && (root_rate == 64000000)) + div = 3; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV); + reg |= BF_CLKCTRL_HBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up AHB divisor\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static struct clk h_clk = { + .parent = &cpu_clk, + .get_rate = h_get_rate, + .set_rate = h_set_rate, + .round_rate = h_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_bits = 31, +}; + +static struct clk ocrom_clk = { + .parent = &h_clk, +}; + +static unsigned long emi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI); + if (clk->parent == &ref_emi_clk) + reg = (reg & BM_CLKCTRL_EMI_DIV_EMI); + else + reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static int emi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_emi_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static unsigned long emi_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_emi_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + if (div > 0xF) + div = 0xF; + return root_rate / div; +} + +static int emi_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + struct mxs_emi_scaling_data emi; + unsigned long iram_phy; + void (*f) (struct mxs_emi_scaling_data *, unsigned int *); + f = iram_alloc((unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale, &iram_phy); + if (NULL == f) { + pr_err("%s Not enough iram\n", __func__); + return -ENOMEM; + } + memcpy(f, mxs_ram_freq_scale, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); +#ifdef CONFIG_MEM_mDDR + if (rate <= 24000000) { + emi.emi_div = 20; + emi.frac_div = 18; + emi.new_freq = 24; + mDDREmiController_24MHz(); + } else if (rate <= 133000000) { + emi.emi_div = 3; + emi.frac_div = 22; + emi.new_freq = 133; + mDDREmiController_133MHz(); + } else { + emi.emi_div = 2; + emi.frac_div = 22; + emi.new_freq = 200; + mDDREmiController_200MHz(); + } +#else + if (rate <= 133000000) { + emi.emi_div = 3; + emi.frac_div = 22; + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + } else if (rate <= 166000000) { + emi.emi_div = 2; + emi.frac_div = 27; + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + } else { + emi.emi_div = 2; + emi.frac_div = 22; + emi.new_freq = 200; + DDR2EmiController_EDE1116_200MHz(); + } +#endif + + local_irq_disable(); + local_fiq_disable(); + f(&emi, get_current_emidata()); + local_fiq_enable(); + local_irq_enable(); + iram_free(iram_phy, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); + + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + + if (!i) { + printk(KERN_ERR "couldn't set up EMI divisor\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static struct clk emi_clk = { + .parent = &ref_emi_clk, + .get_rate = emi_get_rate, + .set_rate = emi_set_rate, + .round_rate = emi_round_rate, + .set_parent = emi_set_parent, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .enable_bits = BM_CLKCTRL_EMI_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .busy_bits = 28, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 7, +}; + +static unsigned long ssp_get_rate(struct clk *clk); + +static int ssp_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + int div = (clk_get_rate(clk->parent) + rate - 1) / rate; + u32 reg_frac; + const int mask = 0x1FF; + int try = 10; + int i = -1; + + if (div == 0 || div > mask) + goto out; + + reg_frac = __raw_readl(clk->scale_reg); + reg_frac &= ~(mask << clk->scale_bits); + + while (try--) { + __raw_writel(reg_frac | (div << clk->scale_bits), + clk->scale_reg); + + if (clk->busy_reg) { + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + } + if (i) + break; + } + + if (!i) + ret = -ETIMEDOUT; + else + ret = 0; + +out: + if (ret != 0) + pr_err("%s: error %d\n", __func__, ret); + return ret; +} + +static int ssp_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk[0] || parent == &ref_io_clk[1]) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; + ret = 0; + } + + return ret; +} + +static struct clk ssp_clk[] = { + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .enable_bits = BM_CLKCTRL_SSP0_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 3, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .enable_bits = BM_CLKCTRL_SSP1_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 4, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .enable_bits = BM_CLKCTRL_SSP2_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 5, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .enable_bits = BM_CLKCTRL_SSP3_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 6, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, +}; + +static unsigned long ssp_get_rate(struct clk *clk) +{ + unsigned int reg, div; + switch (clk - ssp_clk) { + case 0: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); + div = reg & BM_CLKCTRL_SSP0_DIV; + reg &= BM_CLKCTRL_SSP0_DIV_FRAC_EN; + break; + case 1: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); + div = reg & BM_CLKCTRL_SSP1_DIV; + reg &= BM_CLKCTRL_SSP1_DIV_FRAC_EN; + break; + case 2: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); + div = reg & BM_CLKCTRL_SSP2_DIV; + reg &= BM_CLKCTRL_SSP2_DIV_FRAC_EN; + break; + case 3: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); + div = reg & BM_CLKCTRL_SSP3_DIV; + reg &= BM_CLKCTRL_SSP3_DIV_FRAC_EN; + break; + default: + return 0; + } + if (!reg) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x200) / div; +} + +static unsigned long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->get_rate(clk->parent); + long div; + + div = __raw_readl(clk->scale_reg); + if (!(div & BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN)) { + div = (div >> clk->scale_bits) & BM_CLKCTRL_DIS_LCDIF_DIV; + return rate / (div ? div : 1); + } + + div = (div >> clk->scale_bits) & BM_CLKCTRL_DIS_LCDIF_DIV; + rate /= (BM_CLKCTRL_DIS_LCDIF_DIV >> clk->scale_bits) + 1; + rate *= div; + return rate; +} + +static int lcdif_set_rate(struct clk *clk, unsigned long rate) +{ + int reg_val; + + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_DIS_LCDIF_DIV | BM_CLKCTRL_DIS_LCDIF_CLKGATE); + reg_val |= (1 << BP_CLKCTRL_DIS_LCDIF_DIV) & BM_CLKCTRL_DIS_LCDIF_DIV; + __raw_writel(reg_val, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + } + + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + reg_val |= BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF; + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + + return 0; +} + +static int lcdif_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_pix_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static struct clk dis_lcdif_clk = { + .parent = &pll_clk[0], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .busy_bits = 29, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .enable_bits = 31, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 14, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, + .set_parent = lcdif_set_parent, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long hsadc_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + reg = (reg & BM_CLKCTRL_HSADC_FREQDIV) >> BP_CLKCTRL_HSADC_FREQDIV; + return clk->parent->get_rate(clk->parent) / ((1 << reg) * 9); +} + +static int hsadc_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg = clk->parent->get_rate(clk->parent); + if ((reg / rate) % 9) + return -EINVAL; + reg = reg / 9; + switch (reg) { + case 1: + reg = BM_CLKCTRL_HSADC_RESETB; + break; + case 2: + reg = 1 | BM_CLKCTRL_HSADC_RESETB; + break; + case 4: + reg = 2 | BM_CLKCTRL_HSADC_RESETB; + break; + case 8: + reg = 3 | BM_CLKCTRL_HSADC_RESETB; + break; + default: + return -EINVAL; + } + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + return 0; +} + +static unsigned long hsadc_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg = clk->parent->get_rate(clk->parent); + div = ((reg / rate) + 8) / 9; + if (div <= 1) + return reg; + if (div > 4) + return reg >> 3; + if (div > 2) + return reg >> 2; + return reg >> 1; +} + +static struct clk hsadc_clk = { + .parent = &ref_hsadc_clk, + .get_rate = hsadc_get_rate, + .set_rate = hsadc_set_rate, + .round_rate = hsadc_round_rate, +}; + +static unsigned long gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & + BM_CLKCTRL_GPMI_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static int gpmi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_gpmi_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static unsigned long gpmi_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static int gpmi_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return -EINVAL; + + if (root_rate % rate) { + div = mx28_get_frac_div(root_rate / 1000, rate / 1000, 0x3FF); + if (((root_rate / 0x400) * div) > rate) + return -EINVAL; + } + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN); + if (root_rate % rate) + reg |= BM_CLKCTRL_GPMI_DIV_FRAC_EN; + reg |= BF_CLKCTRL_GPMI_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + + do { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + } while (reg & BM_CLKCTRL_GPMI_BUSY); + return 0; +} + +static struct clk gpmi_clk = { + .parent = &ref_gpmi_clk, + .set_parent = gpmi_set_parent, + .get_rate = gpmi_get_rate, + .set_rate = gpmi_set_rate, + .round_rate = gpmi_round_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .enable_bits = BM_CLKCTRL_GPMI_CLKGATE, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 2, +}; + +static unsigned long saif_get_rate(struct clk *clk); +static unsigned long saif_set_rate(struct clk *clk, unsigned int rate); +static unsigned long saif_set_parent(struct clk *clk, struct clk *parent); + +static struct clk saif_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .enable_bits = BM_CLKCTRL_SAIF0_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .busy_bits = 29, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 0, + .set_rate = saif_set_rate, + .set_parent = saif_set_parent, + }, + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .enable_bits = BM_CLKCTRL_SAIF1_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .busy_bits = 29, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 1, + .set_rate = saif_set_rate, + .set_parent = saif_set_parent, + }, +}; + +static unsigned long saif_get_rate(struct clk *clk) +{ + unsigned long reg, div; + if (clk == saif_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); + div = reg & BM_CLKCTRL_SAIF0_DIV; + reg &= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); + div = reg & BM_CLKCTRL_SAIF1_DIV; + reg &= BM_CLKCTRL_SAIF1_DIV_FRAC_EN; + } + if (!reg) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x10000) * div; +} + +static unsigned long saif_set_rate(struct clk *clk, unsigned int rate) +{ + u16 div = 0; + u32 clkctrl_saif; + u64 rates; + struct clk *parent = clk->parent; + + pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, + clk_get_rate(parent)); + + if (rate > clk_get_rate(parent)) + return -EINVAL; + /*saif clock always use frac div*/ + rates = 65536 * (u64)rate; + rates = rates + (u64)(clk_get_rate(parent) / 2); + do_div(rates, clk_get_rate(parent)); + div = rates; + + pr_debug("%s: div calculated is %d\n", __func__, div); + if (!div) + return -EINVAL; + + clkctrl_saif = __raw_readl(clk->scale_reg); + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_DIV; + clkctrl_saif |= div; + clkctrl_saif |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_CLKGATE; + __raw_writel(clkctrl_saif, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + pr_err("couldn't set up SAIF clk divisor\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static unsigned long saif_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + int shift = 4; + /*bypass*/ + if (parent == &pll_clk[0]) + shift = 8; + if (clk->bypass_reg) { + __raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift); + ret = 0; + } + return ret; +} + +static int saif_mclk_enable(struct clk *clk) +{ + /*Check if enabled already*/ + if (__raw_readl(clk->busy_reg) & clk->busy_bits) + return 0; + /*Enable saif to enable mclk*/ + __raw_writel(0x1, clk->enable_reg); + mdelay(1); + __raw_writel(0x1, clk->enable_reg); + mdelay(1); + return 0; +} + +static int saif_mclk_disable(struct clk *clk) +{ + /*Check if disabled already*/ + if (!(__raw_readl(clk->busy_reg) & clk->busy_bits)) + return 0; + /*Disable saif to disable mclk*/ + __raw_writel(0x0, clk->enable_reg); + mdelay(1); + __raw_writel(0x0, clk->enable_reg); + mdelay(1); + return 0; +} + +static struct clk saif_mclk[] = { + { + .parent = &saif_clk[0], + .enable = saif_mclk_enable, + .disable = saif_mclk_disable, + .enable_reg = SAIF0_CTRL, + .enable_bits = BM_SAIF_CTRL_RUN, + .busy_reg = SAIF0_STAT, + .busy_bits = BM_SAIF_STAT_BUSY, + }, + { + .parent = &saif_clk[1], + .enable = saif_mclk_enable, + .disable = saif_mclk_disable, + .enable_reg = SAIF1_CTRL, + .enable_bits = BM_SAIF_CTRL_RUN, + .busy_reg = SAIF1_STAT, + .busy_bits = BM_SAIF_STAT_BUSY, + }, +}; + +static unsigned long pcmspdif_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 4; +} + +static struct clk pcmspdif_clk = { + .parent = &pll_clk[0], + .get_rate = pcmspdif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF, + .enable_bits = BM_CLKCTRL_SPDIF_CLKGATE, +}; + +/* usb_clk for usb0 */ +static struct clk usb_clk0 = { + .parent = &pll_clk[0], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB0_CLKGATE, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb_clk for usb1 */ +static struct clk usb_clk1 = { + .parent = &pll_clk[1], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB1_CLKGATE, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb phy clock for usb0 */ +static struct clk usb_phy_clk0 = { + .parent = &pll_clk[0], + .enable = mx28_raw_disable, /* EN_USB_CLKS = 1 means ON */ + .disable = mx28_raw_enable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_SET, + .enable_bits = BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb phy clock for usb1 */ +static struct clk usb_phy_clk1 = { + .parent = &pll_clk[1], + .enable = mx28_raw_disable, + .disable = mx28_raw_enable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_SET, + .enable_bits = BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk enet_out_clk = { + .parent = &pll_clk[2], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET, + .enable_bits = BM_CLKCTRL_ENET_DISABLE, +}; + +static struct clk_lookup onchip_clocks[] = { + { + .con_id = "xtal.0", + .clk = &xtal_clk[0], + }, + { + .con_id = "xtal.1", + .clk = &xtal_clk[1], + }, + { + .con_id = "xtal.2", + .clk = &xtal_clk[2], + }, + { + .con_id = "pll.0", + .clk = &pll_clk[0], + }, + { + .con_id = "pll.1", + .clk = &pll_clk[1], + }, + { + .con_id = "pll.2", + .clk = &pll_clk[2], + }, + { + .con_id = "ref_xtal", + .clk = &ref_xtal_clk, + }, + { + .con_id = "ref_cpu", + .clk = &ref_cpu_clk, + }, + { + .con_id = "ref_emi", + .clk = &ref_emi_clk, + }, + { + .con_id = "ref_io.0", + .clk = &ref_io_clk[0], + }, + { + .con_id = "ref_io.1", + .clk = &ref_io_clk[1], + }, + { + .con_id = "ref_pix", + .clk = &ref_pix_clk, + }, + { + .con_id = "ref_hsadc", + .clk = &ref_hsadc_clk, + }, + { + .con_id = "ref_gpmi", + .clk = &ref_gpmi_clk, + }, + { + .con_id = "ana", + .clk = &ana_clk, + }, + { + .con_id = "rtc", + .clk = &rtc_clk, + }, + { + .con_id = "cpu", + .clk = &cpu_clk, + }, + { + .con_id = "h", + .clk = &h_clk, + }, + { + .con_id = "x", + .clk = &x_clk, + }, + { + .con_id = "ocrom", + .clk = &ocrom_clk, + }, + { + .con_id = "clk_32k", + .clk = &clk_32k, + }, + { + .con_id = "uart", + .clk = &uart_clk, + }, + { + .con_id = "pwm", + .clk = &pwm_clk, + }, + { + .con_id = "lradc", + .clk = &lradc_clk, + }, + { + .con_id = "ssp.0", + .clk = &ssp_clk[0], + }, + { + .con_id = "ssp.1", + .clk = &ssp_clk[1], + }, + { + .con_id = "ssp.2", + .clk = &ssp_clk[2], + }, + { + .con_id = "ssp.3", + .clk = &ssp_clk[3], + }, + { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, + { + .con_id = "spdif", + .clk = &pcmspdif_clk, + }, + { + .con_id = "saif.0", + .clk = &saif_clk[0], + }, + { + .con_id = "saif.1", + .clk = &saif_clk[1], + }, + { + .con_id = "emi", + .clk = &emi_clk, + }, + { + .con_id = "dis_lcdif", + .clk = &dis_lcdif_clk, + }, + { + .con_id = "hsadc", + .clk = &hsadc_clk, + }, + { + .con_id = "can_clk", + .dev_id = "FlexCAN.0", + .clk = &flexcan_clk[0], + }, + { + .con_id = "can_clk", + .dev_id = "FlexCAN.1", + .clk = &flexcan_clk[1], + }, + { + .con_id = "usb_clk0", + .clk = &usb_clk0, + }, + { + .con_id = "usb_clk1", + .clk = &usb_clk1, + }, + { + .con_id = "usb_phy_clk0", + .clk = &usb_phy_clk0, + }, + { + .con_id = "usb_phy_clk1", + .clk = &usb_phy_clk1, + }, + { + .con_id = "fec_clk", + .clk = &enet_out_clk, + }, + { + .con_id = "saif_mclk.0", + .clk = &saif_mclk[0], + }, + { + .con_id = "saif_mclk.1", + .clk = &saif_mclk[1], + } +}; + +static void mx28_clock_scan(void) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) + cpu_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) + dis_lcdif_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + emi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) + ssp_clk[3].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) + ssp_clk[2].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) + ssp_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) + ssp_clk[0].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) + gpmi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) + saif_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) + saif_clk[0].parent = &ref_xtal_clk; +}; + +void __init mx28_set_input_clk(unsigned long xtal0, + unsigned long xtal1, + unsigned long xtal2, unsigned long enet) +{ + xtal_clk_rate[0] = xtal0; + xtal_clk_rate[1] = xtal1; + xtal_clk_rate[2] = xtal2; + enet_mii_phy_rate = enet; +} + +void mx28_enet_clk_hook(void) +{ + unsigned long reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + + reg &= ~BM_CLKCTRL_ENET_SLEEP; + reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; + /* select clock for 1588 module */ + reg &= ~(BM_CLKCTRL_ENET_DIV_TIME | BM_CLKCTRL_ENET_TIME_SEL); + reg |= BF_CLKCTRL_ENET_TIME_SEL(BV_CLKCTRL_ENET_TIME_SEL__PLL) + | BF_CLKCTRL_ENET_DIV_TIME(12); + + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); +} + +void __init mx28_clock_init(void) +{ + int i; + mx28_clock_scan(); + mx28_enet_clk_hook(); + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) + clk_register(&onchip_clocks[i]); + + clk_enable(&cpu_clk); + clk_enable(&emi_clk); + + clk_en_public_h_asm_ctrl(mx28_enable_h_autoslow, + mx28_set_hbus_autoslow_flags); +} diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c new file mode 100644 index 000000000000..410928fc7d32 --- /dev/null +++ b/arch/arm/mach-mx28/device.c @@ -0,0 +1,1704 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/phy.h> +#include <linux/etherdevice.h> +#include <linux/fec.h> +#include <linux/gpmi-nfc.h> +#include <linux/fsl_devices.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/regs-timrot.h> +#include <mach/regs-lradc.h> +#include <mach/regs-ocotp.h> +#include <mach/device.h> +#include <mach/dma.h> +#include <mach/lradc.h> +#include <mach/lcdif.h> +#include <mach/ddi_bc.h> +#include <mach/pinctrl.h> + +#include "regs-digctl.h" +#include "device.h" +#include "mx28evk.h" +#include "mx28_pins.h" + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct resource duart_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DUART_PHYS_ADDR, + .end = DUART_PHYS_ADDR + 0x1000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_DUART, + .end = IRQ_DUART, + }, +}; + +static void __init mx28_init_duart(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-duart", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = duart_resource; + pdev->num_resources = ARRAY_SIZE(duart_resource); + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_duart(void) +{ +} +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct resource mxs_ahb_apbh_res = { + .flags = IORESOURCE_MEM, + .start = APBH_DMA_PHYS_ADDR, + .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = 16, +}; + +static struct resource mxs_ahb_apbx_res = { + .flags = IORESOURCE_MEM, + .start = APBX_DMA_PHYS_ADDR, + .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbx_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBX, + .chan_num = 16, +}; + +static void __init mx28_init_dma(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + lookup = mxs_get_devices("mxs-dma"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + if (!strcmp(pdev->name, "mxs-dma-apbh")) { + pdev->resource = &mxs_ahb_apbh_res; + pdev->dev.platform_data = &mxs_ahb_apbh_data; + } else if (!strcmp(pdev->name, "mxs-dma-apbx")) { + pdev->resource = &mxs_ahb_apbx_res; + pdev->dev.platform_data = &mxs_ahb_apbx_data; + } else + continue; + pdev->num_resources = 1; + mxs_add_device(pdev, 0); + } +} +#else +static void mx28_init_dma(void) +{ + ; +} +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) +static struct resource framebuffer_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = LCDIF_PHYS_ADDR, + .end = LCDIF_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF, + .end = IRQ_LCDIF, + }, +}; + +static struct mxs_platform_fb_data mxs_framebuffer_pdata = { + .list = LIST_HEAD_INIT(mxs_framebuffer_pdata.list), +}; + +static void __init mx28_init_lcdif(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = framebuffer_resource; + pdev->num_resources = ARRAY_SIZE(framebuffer_resource); + pdev->dev.platform_data = &mxs_framebuffer_pdata; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_lcdif(void) +{ + ; +} +#endif + +#if defined(CONFIG_VIDEO_MXS_PXP) || \ + defined(CONFIG_VIDEO_MXS_PXP_MODULE) +static struct resource pxp_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR), + .end = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR) + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_PXP, + .end = IRQ_PXP, + }, +}; +static void __init mx28_init_pxp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-pxp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = pxp_resource; + pdev->num_resources = ARRAY_SIZE(pxp_resource); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_pxp(void) +{ + ; +} +#endif + +#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE) +struct resource viim_resources[] = { + [0] = { + .start = DIGCTL_PHYS_ADDR, + .end = DIGCTL_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OCOTP_PHYS_ADDR, + .end = OCOTP_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static void __init mx28_init_viim(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs_viim", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = viim_resources; + pdev->num_resources = ARRAY_SIZE(viim_resources); + + mxs_add_device(pdev, 2); +} +#else +static void __init mx28_init_viim(void) +{ +} +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) +#ifdef CONFIG_I2C_MXS_SELECT0 +static struct resource i2c0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = I2C0_PHYS_ADDR, + .end = I2C0_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_I2C0, + .end = MXS_DMA_CHANNEL_AHB_APBX_I2C0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C0_ERROR, + .end = IRQ_I2C0_ERROR, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C0_DMA, + .end = IRQ_I2C0_DMA, + }, +}; + +static struct mxs_i2c_plat_data i2c0_platdata = { +#ifdef CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE + .pioqueue_mode = 1, +#endif +}; +#endif + +#ifdef CONFIG_I2C_MXS_SELECT1 +static struct resource i2c1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = I2C1_PHYS_ADDR, + .end = I2C1_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_I2C1, + .end = MXS_DMA_CHANNEL_AHB_APBX_I2C1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C1_ERROR, + .end = IRQ_I2C1_ERROR, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C1_DMA, + .end = IRQ_I2C1_DMA, + }, +}; + +static struct mxs_i2c_plat_data i2c1_platdata = { +#ifdef CONFIG_I2C_MXS_SELECT1_PIOQUEUE_MODE + .pioqueue_mode = 1, +#endif +}; +#endif + +static void __init mx28_init_i2c(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + + lookup = mxs_get_devices("mxs-i2c"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_I2C_MXS_SELECT0 + case 0: + pdev->resource = i2c0_resource; + pdev->num_resources = ARRAY_SIZE(i2c0_resource); + pdev->dev.platform_data = &i2c0_platdata; + break; +#endif +#ifdef CONFIG_I2C_MXS_SELECT1 + case 1: + pdev->resource = i2c1_resource; + pdev->num_resources = ARRAY_SIZE(i2c1_resource); + pdev->dev.platform_data = &i2c1_platdata; + break; +#endif + default: + return; + } + mxs_add_device(pdev, 2); + } +} +#else +static void __init mx28_init_i2c(void) +{ +} +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) + +extern int enable_gpmi; + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + return !enable_gpmi; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 1, + .boot_rom_version = 1, + .clock_name = "gpmi", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_PHYS_ADDR, + .end = GPMI_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI, + .end = IRQ_GPMI, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_PHYS_ADDR, + .end = BCH_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_BCH, + .end = IRQ_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, +}; + +static void __init mx28_init_gpmi_nfc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &gpmi_nfc_platform_data; + pdev->resource = gpmi_nfc_resources; + pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources); + mxs_add_device(pdev, 1); +} +#else +static void mx28_init_gpmi_nfc(void) +{ +} +#endif + +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +#if defined(CONFIG_MACH_MX28EVK) +#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) +#define MMC1_POWER MXS_PIN_TO_GPIO(PINID_PWM4) +#define MMC0_WP MXS_PIN_TO_GPIO(PINID_SSP1_SCK) +#define MMC1_WP MXS_PIN_TO_GPIO(PINID_GPMI_RESETN) +#endif + +static int mxs_mmc_get_wp_ssp0(void) +{ + return gpio_get_value(MMC0_WP); +} + +static int mxs_mmc_hw_init_ssp0(void) +{ + int ret = 0; + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC0_WP, "mmc0_wp"); + if (ret) + goto out_wp; + + gpio_set_value(MMC0_WP, 0); + gpio_direction_input(MMC0_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC0_POWER, "mmc0_power"); + if (ret) + goto out_power; + + gpio_direction_output(MMC0_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC0_WP); +out_wp: + return ret; +} + +static void mxs_mmc_hw_release_ssp0(void) +{ + gpio_free(MMC0_POWER); + gpio_free(MMC0_WP); + +} + +static void mxs_mmc_cmd_pullup_ssp0(int enable) +{ + mxs_set_pullup(PINID_SSP0_CMD, enable, "mmc0_cmd"); +} + +static unsigned long mxs_mmc_setclock_ssp0(unsigned long hz) +{ + struct clk *ssp = clk_get(NULL, "ssp.0"), *parent; + + if (hz > 1000000) + parent = clk_get(NULL, "ref_io.0"); + else + parent = clk_get(NULL, "xtal.0"); + + clk_set_parent(ssp, parent); + clk_set_rate(ssp, 2 * hz); + clk_put(parent); + clk_put(ssp); + + return hz; +} + +static int mxs_mmc_get_wp_ssp1(void) +{ + return gpio_get_value(MMC1_WP); +} + +static int mxs_mmc_hw_init_ssp1(void) +{ + int ret = 0; + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC1_WP, "mmc1_wp"); + if (ret) + goto out_wp; + + gpio_set_value(MMC1_WP, 0); + gpio_direction_input(MMC1_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC1_POWER, "mmc1_power"); + if (ret) + goto out_power; + + gpio_direction_output(MMC1_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC1_WP); +out_wp: + return ret; +} + +static void mxs_mmc_hw_release_ssp1(void) +{ + gpio_free(MMC1_POWER); + gpio_free(MMC1_WP); +} + +static void mxs_mmc_cmd_pullup_ssp1(int enable) +{ + mxs_set_pullup(PINID_GPMI_RDY1, enable, "mmc1_cmd"); +} + +static unsigned long mxs_mmc_setclock_ssp1(unsigned long hz) +{ + struct clk *ssp = clk_get(NULL, "ssp.1"), *parent; + + if (hz > 1000000) + parent = clk_get(NULL, "ref_io.0"); + else + parent = clk_get(NULL, "xtal.0"); + + clk_set_parent(ssp, parent); + clk_set_rate(ssp, 2 * hz); + clk_put(parent); + clk_put(ssp); + + return hz; +} + +static struct mxs_mmc_platform_data mmc0_data = { + .hw_init = mxs_mmc_hw_init_ssp0, + .hw_release = mxs_mmc_hw_release_ssp0, + .get_wp = mxs_mmc_get_wp_ssp0, + .cmd_pullup = mxs_mmc_cmd_pullup_ssp0, + .setclock = mxs_mmc_setclock_ssp0, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 48000000, + .read_uA = 50000, + .write_uA = 70000, + .clock_mmc = "ssp.0", + .power_mmc = NULL, +}; + +static struct resource mmc0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = SSP0_PHYS_ADDR, + .end = SSP0_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP0, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP0_DMA, + .end = IRQ_SSP0_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP0, + .end = IRQ_SSP0, + }, +}; + +static struct mxs_mmc_platform_data mmc1_data = { + .hw_init = mxs_mmc_hw_init_ssp1, + .hw_release = mxs_mmc_hw_release_ssp1, + .get_wp = mxs_mmc_get_wp_ssp1, + .cmd_pullup = mxs_mmc_cmd_pullup_ssp1, + .setclock = mxs_mmc_setclock_ssp1, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 48000000, + .read_uA = 50000, + .write_uA = 70000, + .clock_mmc = "ssp.1", + .power_mmc = NULL, +}; + +static struct resource mmc1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = SSP1_PHYS_ADDR, + .end = SSP1_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1, + .end = IRQ_SSP1, + }, +}; + +static void __init mx28_init_mmc(void) +{ + struct platform_device *pdev; + + if (mxs_get_type(PINID_SSP0_CMD) == PIN_FUN1) { + pdev = mxs_get_device("mxs-mmc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mmc0_resource; + pdev->num_resources = ARRAY_SIZE(mmc0_resource); + pdev->dev.platform_data = &mmc0_data; + mxs_add_device(pdev, 2); + } + + if (mxs_get_type(PINID_GPMI_RDY1) == PIN_FUN2) { + pdev = mxs_get_device("mxs-mmc", 1); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mmc1_resource; + pdev->num_resources = ARRAY_SIZE(mmc1_resource); + pdev->dev.platform_data = &mmc1_data; + mxs_add_device(pdev, 2); + } +} +#else +static void mx28_init_mmc(void) +{ +} +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct mxs_spi_platform_data spi_data = { + .clk = "ssp.2", +}; +static struct resource ssp2_resources[] = { + { + .start = SSP2_PHYS_ADDR, + .end = SSP2_PHYS_ADDR + 0x2000 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP2, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP2, + .flags = IORESOURCE_DMA, + }, { + .start = IRQ_SSP2_DMA, + .end = IRQ_SSP2_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_SSP2, + .end = IRQ_SSP2, + .flags = IORESOURCE_IRQ, + }, +}; + +static void __init mx28_init_spi(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-spi", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = ssp2_resources; + pdev->num_resources = ARRAY_SIZE(ssp2_resources); + pdev->dev.platform_data = &spi_data; + + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_spi(void) +{ +} +#endif + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) +static struct resource mx28_wdt_res = { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, +}; + +static void __init mx28_init_wdt(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-wdt", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = &mx28_wdt_res; + pdev->num_resources = 1; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_wdt(void) +{ + ; +} +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) +static struct resource mx28_rtc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_1MSEC, + .end = IRQ_RTC_1MSEC, + }, +}; + +static void __init mx28_init_rtc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-rtc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_rtc_res; + pdev->num_resources = ARRAY_SIZE(mx28_rtc_res); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_rtc(void) +{ + ; +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +static struct resource fec0_resource[] = { + { + .start = ENET_PHYS_ADDR, + .end = ENET_PHYS_ADDR + 0x3fff, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_MAC0, + .end = IRQ_ENET_MAC0, + .flags = IORESOURCE_IRQ + }, +}; + +static struct resource fec1_resource[] = { + { + .start = ENET_PHYS_ADDR + 0x4000, + .end = ENET_PHYS_ADDR + 0x7fff, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_MAC1, + .end = IRQ_ENET_MAC1, + .flags = IORESOURCE_IRQ + }, +}; + +extern int mx28evk_enet_gpio_init(void); +static struct fec_platform_data fec_pdata0 = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct fec_platform_data fec_pdata1 = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static void __init mx28_init_fec(void) +{ + struct platform_device *pdev; + struct mxs_dev_lookup *lookup; + struct fec_platform_data *pfec; + int i; + u32 val; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + lookup = mxs_get_devices("mxs-fec"); + if (lookup == NULL || IS_ERR(lookup)) + return; + + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + switch (pdev->id) { + case 0: + pdev->resource = fec0_resource; + pdev->num_resources = ARRAY_SIZE(fec0_resource); + pdev->dev.platform_data = &fec_pdata0; + break; + case 1: + pdev->resource = fec1_resource; + pdev->num_resources = ARRAY_SIZE(fec1_resource); + pdev->dev.platform_data = &fec_pdata1; + break; + default: + return; + } + + pfec = (struct fec_platform_data *)pdev->dev.platform_data; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + + mxs_add_device(pdev, 2); + } +} +#else +static void __init mx28_init_fec(void) +{ + ; +} +#endif + +#if defined(CONFIG_FEC_L2SWITCH) +static struct resource l2switch_resources[] = { + { + .start = ENET_PHYS_ADDR, + .end = ENET_PHYS_ADDR + 0x17FFC, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_SWI, + .end = IRQ_ENET_SWI, + .flags = IORESOURCE_IRQ + }, + { + .start = IRQ_ENET_MAC0, + .end = IRQ_ENET_MAC0, + .flags = IORESOURCE_IRQ + }, + { + .start = IRQ_ENET_MAC1, + .end = IRQ_ENET_MAC1, + .flags = IORESOURCE_IRQ + }, +}; + +/* Define the fixed address of the L2 Switch hardware. */ +static unsigned int switch_platform_hw[2] = { + (0x800F8000), + (0x800FC000), +}; + +static struct fec_platform_data fec_enet = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct switch_platform_data l2switch_data = { + .id = 0, + .fec_enet = &fec_enet, + .hash_table = 0, + .switch_hw = switch_platform_hw, +}; + +static void __init mx28_init_l2switch(void) +{ + struct platform_device *pdev; + struct switch_platform_data *pswitch; + struct fec_platform_data *pfec; + u32 val; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + pdev = mxs_get_device("mxs-l2switch", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + pdev->resource = l2switch_resources; + pdev->num_resources = ARRAY_SIZE(l2switch_resources); + pdev->dev.platform_data = &l2switch_data; + + pswitch = (struct switch_platform_data *)pdev->dev.platform_data; + pfec = pswitch->fec_enet; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + + mxs_add_device(pdev, 2); +} +#else +static void __init mx28_init_l2switch(void) +{ + ; +} +#endif + +#ifdef CONFIG_MXS_LRADC +struct mxs_lradc_plat_data mx28_lradc_data = { + .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10, + .battery_voltage = BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7, +}; + +static struct resource mx28_lradc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void __init mx28_init_lradc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-lradc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_lradc_res; + pdev->num_resources = ARRAY_SIZE(mx28_lradc_res); + pdev->dev.platform_data = &mx28_lradc_data; + mxs_add_device(pdev, 0); +} +#else +static void __init mx28_init_lradc(void) +{ + ; +} +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) +static struct mxskbd_keypair keyboard_data[] = { + { 100, KEY_F4 }, + { 306, KEY_F5 }, + { 626, KEY_F6 }, + { 932, KEY_F7 }, + { 1260, KEY_F8 }, + { 1584, KEY_F9 }, + { 1907, KEY_F10 }, + { 2207, KEY_F11 }, + { 2525, KEY_F12 }, + { 2831, KEY_F13}, + { 3134, KEY_F14 }, + { -1, 0 }, +}; + +static struct mxs_kbd_plat_data mxs_kbd_data = { + .keypair = keyboard_data, + .channel = LRADC_CH1, + .btn_enable = BM_LRADC_CTRL0_BUTTON1_DETECT_ENABLE, + .btn_irq_stat = BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ, + .btn_irq_ctrl = BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN, +}; + +static struct resource mx28_kbd_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH1, + .end = IRQ_LRADC_CH1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_BUTTON1, + .end = IRQ_LRADC_BUTTON1, + } +}; + +static void __init mx28_init_kbd(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-kbd", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_kbd_res; + pdev->num_resources = ARRAY_SIZE(mx28_kbd_res); + pdev->dev.platform_data = &mxs_kbd_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_kbd(void) +{ + ; +} +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) +static struct mxs_touchscreen_plat_data mx28_ts_data = { + .x_plus_chan = LRADC_TOUCH_X_PLUS, + .x_minus_chan = LRADC_TOUCH_X_MINUS, + .y_plus_chan = LRADC_TOUCH_Y_PLUS, + .y_minus_chan = LRADC_TOUCH_Y_MINUS, + .x_plus_val = BM_LRADC_CTRL0_XPULSW, + .x_minus_val = BF_LRADC_CTRL0_XNURSW(2), + .y_plus_val = BF_LRADC_CTRL0_YPLLSW(1), + .y_minus_val = BM_LRADC_CTRL0_YNLRSW, + .x_plus_mask = BM_LRADC_CTRL0_XPULSW, + .x_minus_mask = BM_LRADC_CTRL0_XNURSW, + .y_plus_mask = BM_LRADC_CTRL0_YPLLSW, + .y_minus_mask = BM_LRADC_CTRL0_YNLRSW, +}; + +static struct resource mx28_ts_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_TOUCH, + .end = IRQ_LRADC_TOUCH, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH5, + .end = IRQ_LRADC_CH5, + }, +}; + +static void __init mx28_init_ts(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-ts", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_ts_res; + pdev->num_resources = ARRAY_SIZE(mx28_ts_res); + pdev->dev.platform_data = &mx28_ts_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_ts(void) +{ + ; +} +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) +static void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (en) { + if (!pwdn++) + gpio_set_value(MXS_PIN_TO_GPIO(PINID_SSP1_CMD), 1); + } else { + if (!--pwdn) + gpio_set_value(MXS_PIN_TO_GPIO(PINID_SSP1_CMD), 0); + } +} + +struct flexcan_platform_data flexcan_data[] = { + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 2, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, + }, + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 2, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, + }, +}; + +static struct resource flexcan0_resources[] = { + { + .start = CAN0_PHYS_ADDR, + .end = CAN0_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM,}, + { + .start = IRQ_CAN0, + .end = IRQ_CAN0, + .flags = IORESOURCE_IRQ,}, +}; +static struct resource flexcan1_resources[] = { + { + .start = CAN1_PHYS_ADDR, + .end = CAN1_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM,}, + { + .start = IRQ_CAN1, + .end = IRQ_CAN1, + .flags = IORESOURCE_IRQ,}, +}; + +static inline void mx28_init_flexcan(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("FlexCAN", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = flexcan0_resources; + pdev->num_resources = ARRAY_SIZE(flexcan0_resources); + pdev->dev.platform_data = &flexcan_data[0]; + mxs_add_device(pdev, 2); + + pdev = mxs_get_device("FlexCAN", 1); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = flexcan1_resources; + pdev->num_resources = ARRAY_SIZE(flexcan1_resources); + pdev->dev.platform_data = &flexcan_data[1]; + mxs_add_device(pdev, 2); +} +#else +static inline void mx28_init_flexcan(void) +{ +} +#endif +#if defined(CONFIG_BATTERY_MXS) +/* battery info data */ +static ddi_bc_Cfg_t battery_data = { + .u32StateMachinePeriod = 100, /* ms */ + .u16CurrentRampSlope = 75, /* mA/s */ + .u16ConditioningThresholdVoltage = 2900, /* mV */ + .u16ConditioningMaxVoltage = 3000, /* mV */ + .u16ConditioningCurrent = 160, /* mA */ + .u32ConditioningTimeout = 4*60*60*1000, /* ms (4 hours) */ + .u16ChargingVoltage = 4200, /* mV */ + /* FIXME: the current comparator could have h/w bugs in current + * detection through POWER_STS.CHRGSTS bit */ + .u16ChargingCurrent = 600, /* mA 600 */ + .u16ChargingThresholdCurrent = 60, /* mA 60 */ + .u32ChargingTimeout = 4*60*60*1000,/* ms (4 hours) */ + .u32TopOffPeriod = 30*60*1000, /* ms (30 minutes) */ + .monitorDieTemp = 1, /* Monitor the die */ + .u8DieTempHigh = 75, /* deg centigrade */ + .u8DieTempLow = 65, /* deg centigrade */ + .u16DieTempSafeCurrent = 0, /* mA */ + .monitorBatteryTemp = 0, /* Monitor the battery*/ + .u8BatteryTempChannel = 0, /* LRADC 0 */ + .u16BatteryTempHigh = 642, /* Unknown units */ + .u16BatteryTempLow = 497, /* Unknown units */ + .u16BatteryTempSafeCurrent = 0, /* mA */ +}; + +static struct resource battery_resource[] = { + {/* 0 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V, + .end = IRQ_VDD5V, + }, + {/* 1 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_DCDC4P2_BRNOUT, + .end = IRQ_DCDC4P2_BRNOUT, + }, + {/* 2 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_BATT_BRNOUT, + .end = IRQ_BATT_BRNOUT, + }, + {/* 3 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDD_BRNOUT, + .end = IRQ_VDDD_BRNOUT, + }, + {/* 4 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDA_BRNOUT, + .end = IRQ_VDDA_BRNOUT, + }, + {/* 5 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDIO_BRNOUT, + .end = IRQ_VDDIO_BRNOUT, + }, + {/* 6 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V_DROOP, + .end = IRQ_VDD5V_DROOP, + }, +}; + +static void mx28_init_battery(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-battery", 0); + if (pdev) { + pdev->resource = battery_resource, + pdev->num_resources = ARRAY_SIZE(battery_resource), + pdev->dev.platform_data = &battery_data; + mxs_add_device(pdev, 3); + } +} +#else +static void mx28_init_battery(void) +{ +} +#endif + +#if defined(CONFIG_CRYPTO_DEV_DCP) + +static struct resource dcp_resources[] = { + + { + .flags = IORESOURCE_MEM, + .start = DCP_PHYS_ADDR, + .end = DCP_PHYS_ADDR + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP_VMI, + .end = IRQ_DCP_VMI, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP, + .end = IRQ_DCP, + }, +}; + +static void __init mx28_init_dcp(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("dcp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = dcp_resources; + pdev->num_resources = ARRAY_SIZE(dcp_resources); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_dcp(void) +{ + ; +} +#endif + +#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) +static int audio_clk_init(struct clk *clk) +{ + struct clk *pll_clk; + struct clk *saif_mclk0; + struct clk *saif_mclk1; + int ret = -EINVAL; + if (IS_ERR(clk)) { + pr_err("%s:failed to get clk\n", __func__); + goto err_clk_init; + } + pll_clk = clk_get(NULL, "pll.0"); + if (IS_ERR(pll_clk)) { + pr_err("%s:failed to get pll_clk\n", __func__); + goto err_clk_init; + } + saif_mclk0 = clk_get(NULL, "saif_mclk.0"); + if (IS_ERR(saif_mclk0)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_init; + } + saif_mclk1 = clk_get(NULL, "saif_mclk.1"); + if (IS_ERR(saif_mclk1)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_init; + } + ret = clk_set_parent(clk, pll_clk); + if (ret) { + pr_err("%s:failed to set parent clk\n", __func__); + goto err_clk_init; + } + ret = 0; + /*set a default freq of 12M to sgtl5000*/ + clk_set_rate(clk, 12000000); + clk_enable(clk); + /*set the saif clk mux, saif0/saif1 both use saif0 clk*/ + __raw_writel(BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(0x2), \ + IO_ADDRESS(DIGCTL_PHYS_ADDR) + HW_DIGCTL_CTRL); + + /*enable saif0/saif1 clk output*/ + clk_enable(saif_mclk0); + clk_enable(saif_mclk1); +err_clk_init: + return ret; +} + +static int audio_clk_finit(void) +{ + struct clk *saif_clk; + struct clk *saif_mclk0; + struct clk *saif_mclk1; + int ret = 0; + saif_clk = clk_get(NULL, "saif.0"); + if (IS_ERR(saif_clk)) { + pr_err("%s:failed to get saif_clk\n", __func__); + ret = -EINVAL; + goto err_clk_finit; + } + clk_disable(saif_clk); + + saif_mclk0 = clk_get(NULL, "saif_mclk.0"); + if (IS_ERR(saif_mclk0)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_finit; + } + clk_disable(saif_mclk0); + + saif_mclk1 = clk_get(NULL, "saif_mclk.1"); + if (IS_ERR(saif_mclk1)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_finit; + } + clk_disable(saif_mclk1); +err_clk_finit: + return ret; +} + +static struct mxs_audio_platform_data audio_plat_data; +#endif + +#if defined(CONFIG_SND_SOC_SGTL5000) || defined(CONFIG_SND_SOC_SGTL5000_MODULE) +void __init mx28_init_audio(void) +{ struct platform_device *pdev; + pdev = mxs_get_device("mxs-sgtl5000", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + mxs_add_device(pdev, 3); + audio_plat_data.saif_mclock = clk_get(NULL, "saif.0"); + audio_clk_init(audio_plat_data.saif_mclock); + pdev->dev.platform_data = &audio_plat_data; +} +#else +void __init mx28_init_audio(void) +{ +} +#endif + +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) +void __init mx28_init_spdif(void) +{ struct platform_device *pdev; + pdev = mxs_get_device("mxs-spdif", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + mxs_add_device(pdev, 3); +} +#else +static inline mx28_init_spdif(void) +{ +} +#endif + +#if defined(CONFIG_MXS_PERSISTENT) +static const struct mxs_persistent_bit_config +mx28_persistent_bit_config[] = { + { .reg = 0, .start = 0, .width = 1, + .name = "CLOCKSOURCE" }, + { .reg = 0, .start = 1, .width = 1, + .name = "ALARM_WAKE_EN" }, + { .reg = 0, .start = 2, .width = 1, + .name = "ALARM_EN" }, + { .reg = 0, .start = 3, .width = 1, + .name = "CLK_SECS" }, + { .reg = 0, .start = 4, .width = 1, + .name = "XTAL24MHZ_PWRUP" }, + { .reg = 0, .start = 5, .width = 1, + .name = "XTAL32MHZ_PWRUP" }, + { .reg = 0, .start = 6, .width = 1, + .name = "XTAL32_FREQ" }, + { .reg = 0, .start = 7, .width = 1, + .name = "ALARM_WAKE" }, + { .reg = 0, .start = 8, .width = 5, + .name = "MSEC_RES" }, + { .reg = 0, .start = 13, .width = 1, + .name = "DISABLE_XTALOK" }, + { .reg = 0, .start = 14, .width = 2, + .name = "LOWERBIAS" }, + { .reg = 0, .start = 16, .width = 1, + .name = "DISABLE_PSWITCH" }, + { .reg = 0, .start = 17, .width = 1, + .name = "AUTO_RESTART" }, + { .reg = 0, .start = 18, .width = 1, + .name = "ENABLE_LRADC_PWRUP" }, + { .reg = 0, .start = 20, .width = 1, + .name = "THERMAL_RESET" }, + { .reg = 0, .start = 21, .width = 1, + .name = "EXTERNAL_RESET" }, + { .reg = 0, .start = 28, .width = 4, + .name = "ADJ_POSLIMITBUCK" }, + { .reg = 1, .start = 0, .width = 1, + .name = "FORCE_RECOVERY" }, + { .reg = 1, .start = 1, .width = 1, + .name = "ROM_REDUNDANT_BOOT" }, + { .reg = 1, .start = 2, .width = 1, + .name = "NAND_SDK_BLOCK_REWRITE" }, + { .reg = 1, .start = 3, .width = 1, + .name = "SD_SPEED_ENABLE" }, + { .reg = 1, .start = 4, .width = 1, + .name = "SD_INIT_SEQ_1_DISABLE" }, + { .reg = 1, .start = 5, .width = 1, + .name = "SD_CMD0_DISABLE" }, + { .reg = 1, .start = 6, .width = 1, + .name = "SD_INIT_SEQ_2_ENABLE" }, + { .reg = 1, .start = 7, .width = 1, + .name = "OTG_ATL_ROLE_BIT" }, + { .reg = 1, .start = 8, .width = 1, + .name = "OTG_HNP_BIT" }, + { .reg = 1, .start = 9, .width = 1, + .name = "USB_LOW_POWER_MODE" }, + { .reg = 1, .start = 10, .width = 1, + .name = "SKIP_CHECKDISK" }, + { .reg = 1, .start = 11, .width = 1, + .name = "USB_BOOT_PLAYER_MODE" }, + { .reg = 1, .start = 12, .width = 1, + .name = "ENUMERATE_500MA_TWICE" }, + { .reg = 1, .start = 13, .width = 19, + .name = "SPARE_GENERAL" }, + + { .reg = 2, .start = 0, .width = 32, + .name = "SPARE_2" }, + { .reg = 3, .start = 0, .width = 32, + .name = "SPARE_3" }, + { .reg = 4, .start = 0, .width = 32, + .name = "SPARE_4" }, + { .reg = 5, .start = 0, .width = 32, + .name = "SPARE_5" }, +}; + +static struct mxs_platform_persistent_data mx28_persistent_data = { + .bit_config_tab = mx28_persistent_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx28_persistent_bit_config), +}; + +static struct resource mx28_persistent_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void mx28_init_persistent(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-persistent", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx28_persistent_data; + pdev->resource = mx28_persistent_res, + pdev->num_resources = ARRAY_SIZE(mx28_persistent_res), + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_persistent() +{ +} +#endif + +#if defined(CONFIG_MXS_PERFMON) + +static struct mxs_perfmon_bit_config +mx28_perfmon_bit_config[] = { + {.field = (1 << 0), .name = "MID0-PXP" }, + {.field = (1 << 1), .name = "MID1-LCDIF" }, + {.field = (1 << 2), .name = "MID2-BCH" }, + {.field = (1 << 3), .name = "MID3-DCP" } +}; + +static struct mxs_platform_perfmon_data mx28_perfmon_data = { + .bit_config_tab = mx28_perfmon_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx28_perfmon_bit_config), +}; + +static struct resource mx28_perfmon_res[] = { + { + .flags = IORESOURCE_MEM, + .start = PERFMON_PHYS_ADDR, + .end = PERFMON_PHYS_ADDR + 0x1000 - 1, + }, +}; + +static void mx28_init_perfmon(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-perfmon", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx28_perfmon_data; + pdev->resource = mx28_perfmon_res, + pdev->num_resources = ARRAY_SIZE(mx28_perfmon_res), + mxs_add_device(pdev, 3); +} + +#else + +static void mx28_init_perfmon() +{ +} + +#endif + + +#if defined(CONFIG_FSL_OTP) +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3), + BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP), + BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2), + BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .regulator_name = "vddio", + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +static void __init mx28_init_otp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("ocotp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &otp_data; + pdev->resource = NULL; + pdev->num_resources = 0; + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_otp(void) +{ +} +#endif + +int __init mx28_device_init(void) +{ + mx28_init_dma(); + mx28_init_viim(); + mx28_init_duart(); + mx28_init_i2c(); + mx28_init_lradc(); + mx28_init_auart(); + mx28_init_mmc(); + mx28_init_spi(); + mx28_init_gpmi_nfc(); + mx28_init_wdt(); + mx28_init_rtc(); + mx28_init_fec(); + mx28_init_l2switch(); + mx28_init_flexcan(); + mx28_init_kbd(); + mx28_init_ts(); + mx28_init_audio(); + mx28_init_spdif(); + mx28_init_lcdif(); + mx28_init_pxp(); + mx28_init_dcp(); + mx28_init_battery(); + mx28_init_persistent(); + mx28_init_perfmon(); + mx28_init_otp(); + return 0; +} + +static struct __initdata map_desc mx28_io_desc[] = { + { + .virtual = MX28_SOC_IO_VIRT_BASE, + .pfn = __phys_to_pfn(MX28_SOC_IO_PHYS_BASE), + .length = MX28_SOC_IO_AREA_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = MX28_OCRAM_BASE, + .pfn = __phys_to_pfn(MX28_OCRAM_PHBASE), + .length = MX28_OCRAM_SIZE, + .type = MT_DEVICE, + } +}; + +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} + +void __init mx28_irq_init(void) +{ + avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS); +} + +static void mx28_timer_init(void) +{ + int i, reg; + mx28_clock_init(); + + mx28_timer.clk = clk_get(NULL, "clk_32k"); + if (mx28_timer.clk == NULL || IS_ERR(mx28_timer.clk)) + return; + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + for (i = 0; i < 10000; i++) { + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + if (!(reg & BM_TIMROT_ROTCTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return; + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + for (i = 0; i < 4; i++) { + if (!(reg & (BM_TIMROT_ROTCTRL_TIM0_PRESENT << i))) + continue; + mx28_timer.id = i; + mx28_timer.irq = IRQ_TIMER0 + i; + mxs_timer_init(&mx28_timer); + return; + } +} + +struct mxs_sys_timer mx28_timer = { + .timer = { + .init = mx28_timer_init, + }, + .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL, + .base = IO_ADDRESS(TIMROT_PHYS_ADDR), +}; + diff --git a/arch/arm/mach-mx28/device.h b/arch/arm/mach-mx28/device.h new file mode 100644 index 000000000000..6fac8f670c58 --- /dev/null +++ b/arch/arm/mach-mx28/device.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DEVICE_H__ +#define __ASM_ARCH_MACH_DEVICE_H__ + +extern struct mxs_sys_timer mx28_timer; + +extern void __init mx28_map_io(void); +extern void __init mx28_clock_init(void); +extern void __init mx28_irq_init(void); +extern int __init mx28_pinctrl_init(void); +extern int __init mx28_gpio_init(void); +extern int __init mx28_device_init(void); +extern void __init mx28_init_auart(void); +extern void __init +mx28_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long); + +#endif diff --git a/arch/arm/mach-mx28/emi.S b/arch/arm/mach-mx28/emi.S new file mode 100644 index 000000000000..ec25b4e942e5 --- /dev/null +++ b/arch/arm/mach-mx28/emi.S @@ -0,0 +1,220 @@ +/* + * Freescale MX28 low level RAM frequency manipulation + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/system.h> +#include <asm/pgtable-hwdef.h> + +#include <mach/hardware.h> +#include <mach/regs-power.h> +#include "regs-clkctrl.h" +#include "regs-dram.h" +#include "regs-digctl.h" + +#include "emi_settings.h" + +.global cpu_arm926_switch_mm + +.align 8 +ENTRY(mxs_ram_freq_scale) + stmfd sp!, {r1 - r10, lr} + ldr r5, [r0, #SCALING_DATA_NEW_FREQ_OFFSET] + ldr r6, [r0, #SCALING_DATA_CUR_FREQ_OFFSET] + ldr r7, [r0, #SCALING_DATA_EMI_DIV_OFFSET] + mov r7, r7, LSL #BP_CLKCTRL_EMI_DIV_EMI + ldr r8, [r0, #SCALING_DATA_FRAC_DIV_OFFSET] + mov r8, r8, LSL #BP_CLKCTRL_FRAC0_EMIFRAC + + @copy memory setting to iram + mov r2, #MX28_DRAMCTRLREGNUM + adr r0, __mx28_emisetting +1: ldr r3, [r1] + str r3, [r0] + add r0, r0, #4 + add r1, r1, #4 + subs r2, r2, #1 + bne 1b + + @set temp static to iram. + adr r9, __mxs_temp_stack + + @ clean cache + ldr r1, __mxs_flush_cache_addr + mov lr, pc + mov pc, r1 + + mov r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF00 + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF0000 + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF000000 + + mov r0, r2 + bl lock_vector_tlb + + mov r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF00 + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF0000 + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF000000 + + @ Make sure emi not busy +2: + ldr r1, [r0, #HW_DRAM_CTL08] + tst r1, #BM_DRAM_CTL08_CONTROLLER_BUSY + bne 2b + + @ put DRAM into self refresh + ldr r1, [r0, #HW_DRAM_CTL17] + orr r1, r1, #BM_DRAM_CTL17_SREFRESH + str r1, [r0, #HW_DRAM_CTL17] +3: + ldr r1, [r0, #HW_DRAM_CTL172] + tst r1, #BM_DRAM_CTL172_CKE_STATUS + beq 3b + + ldr r1, [r0, #HW_DRAM_CTL58] + orr r1, #BF_DRAM_CTL58_INT_MASK(0x100) + str r1, [r0, #HW_DRAM_CTL58] + + @stop emi controller + ldr r1, [r0, #HW_DRAM_CTL16] + bic r1, r1, #BM_DRAM_CTL16_START + str r1, [r0, #HW_DRAM_CTL16] + + @clear lock status HW_DRAM_CTL164_CLR(BF_DRAM_CTL164_INT_ACK(0x3ff)); + ldr r1, [r0, #HW_DRAM_CTL164] + bic r1, r1, #BF_DRAM_CTL164_INT_ACK(0xff) + bic r1, r1, #BF_DRAM_CTL164_INT_ACK(0x300) + str r1, [r0, #HW_DRAM_CTL164] + + ldr r1, [r2, #HW_CLKCTRL_FRAC0] + and r1, #BM_CLKCTRL_FRAC0_EMIFRAC + ldr r3, [r2, #HW_CLKCTRL_EMI] + and r3, #BM_CLKCTRL_EMI_DIV_EMI + +/* + * The fractional divider and integer divider must be written in such + * an order to guarantee that when going from a lower frequency to a + * higher frequency that any intermediate frequencies do not exceed + * the final frequency. For this reason, we must make sure to check + * the current divider values with the new divider values and write + * them in the correct order. + */ + + ldr r9, [r2, #HW_CLKCTRL_FRAC0] + bic r9, #BM_CLKCTRL_FRAC0_EMIFRAC + orr r9, r8 + + ldr r10, [r2, #HW_CLKCTRL_EMI] + bic r10, #BM_CLKCTRL_EMI_DIV_EMI + orr r10, r7 + + cmp r8, r1 + strgt r9, [r2, #HW_CLKCTRL_FRAC0] + cmp r7, r3 + strgt r10, [r2, #HW_CLKCTRL_EMI] + + cmp r8, r1 + strlt r9, [r2, #HW_CLKCTRL_FRAC0] + cmp r7, r3 + strlt r10, [r2, #HW_CLKCTRL_EMI] + + @copy memory setting to iram + mov r3, r0 + adr r4, __mx28_emisetting + mov r6, #MX28_DRAMCTRLREGNUM +8: ldr r5, [r4] + str r5, [r3] + add r3, r3, #4 + add r4, r4, #4 + subs r6, r6, #1 + bne 8b + +7: ldr r1, [r2, #HW_CLKCTRL_EMI] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 7b + + @Restart memory controller + ldr r1, [r0, #HW_DRAM_CTL16] + orr r1, #BM_DRAM_CTL16_START + str r1, [r0, #HW_DRAM_CTL16] + + /*Wait DLL is locked*/ +9: + ldr r1, [r0, #HW_DRAM_CTL21] + tst r1, #BM_DRAM_CTL21_DLLLOCKREG + beq 9b + + + @11. Exit Memory self-refresh + ldr r1, [r0, #HW_DRAM_CTL17] + bic r1, r1, #BM_DRAM_CTL17_SREFRESH + str r1, [r0, #HW_DRAM_CTL17] + + @Wait Memory device exit into self-refresh +10: + ldr r1, [r0, #HW_DRAM_CTL172] + tst r1, #BM_DRAM_CTL172_CKE_STATUS + bne 10b + + mov r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF00 + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF0000 + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF000000 + + ldr r0, [r2, #HW_DIGCTL_MICROSECONDS]; + add r0, #100 +11: ldr r1, [r2, #HW_DIGCTL_MICROSECONDS]; + cmp r1, r0 + blt 11b + +@ restore regs and return + ldmfd sp!, {r1 - r10, lr} + mov pc, lr + + .space 0x100 +__mxs_temp_stack: + .word 0 +__mx28_emisetting: + .space MX28_DRAMCTRLREGNUM*4 + +lock_vector_tlb: + mov r1, r0 @ set r1 to the value of the address to be locked down + mcr p15,0,r1,c8,c7,1 @ invalidate TLB single entry to ensure that + @ LockAddr is not already in the TLB + mrc p15,0,r0,c10,c0,0 @ read the lockdown register + orr r0,r0,#1 @ set the preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown register + ldr r1,[r1] @ TLB will miss, and entry will be loaded + mrc p15,0,r0,c10,c0,0 @ read the lockdown register (victim will have + @ incremented) + bic r0,r0,#1 @ clear preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown registerADR r1,LockAddr + mov pc,lr + +__mxs_flush_cache_addr: + .word arm926_flush_kern_cache_all + +ENTRY(mxs_ram_funcs_sz) + .word . - mxs_ram_freq_scale +ENTRY(mxs_ram_freq_scale_end) diff --git a/arch/arm/mach-mx28/emi_settings.c b/arch/arm/mach-mx28/emi_settings.c new file mode 100644 index 000000000000..918e39deb439 --- /dev/null +++ b/arch/arm/mach-mx28/emi_settings.c @@ -0,0 +1,1263 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/phy.h> + +#include <asm/mach/map.h> + +#include <mach/mx28.h> +#include <mach/clock.h> +#include "emi_settings.h" + +static unsigned int DRAM_REG[MX28_DRAMCTRLREGNUM]; +unsigned int *get_current_emidata() +{ + return DRAM_REG; +} + +void test_emi_change() +{ + struct mxs_emi_scaling_data emi; + void (*f) (struct mxs_emi_scaling_data *, unsigned int *); + f = (void *)MX28_OCRAM_BASE; + memcpy(f, mxs_ram_freq_scale, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); + + pr_debug("start change emi frequency test\n"); + pr_debug("begin change 133\n"); + emi.emi_div = 3; /* 130Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 133\n"); + + pr_debug("begin change 166\n"); + emi.emi_div = 2; /* 160Mhz */ + emi.frac_div = 27; /* 320Mhz */ + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 166\n"); + + pr_debug("begin change 200\n"); + emi.emi_div = 2; /* 192Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 200; + DDR2EmiController_EDE1116_200MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 200\n"); + + pr_debug("begin change 166\n"); + emi.emi_div = 2; /* 166Mhz */ + emi.frac_div = 26; /* 332Mhz */ + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 166\n"); + + pr_debug("begin change 133\n"); + emi.emi_div = 3; /* 130Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 133\n"); + pr_debug("finish change emi frequency test\n"); +} + +void DDR2EmiController_EDE1116_133MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x04003603; + DRAM_REG[39] = 0x070000c8; + DRAM_REG[40] = 0x0200682b; + DRAM_REG[41] = 0x00020208; + DRAM_REG[42] = 0x00246c06; + DRAM_REG[43] = 0x02110409; + DRAM_REG[44] = 0x01020202; + DRAM_REG[45] = 0x00c80013; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000409; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x04090409; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf4004a27; + DRAM_REG[72] = 0xf4004a27; + DRAM_REG[73] = 0xf4004a27; + DRAM_REG[74] = 0xf4004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02030303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00040900; + DRAM_REG[180] = 0x04090409; + DRAM_REG[181] = 0x02420242; + DRAM_REG[182] = 0x02420242; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} + +void DDR2EmiController_EDE1116_166MHz(void) +{ + + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x06004303; + DRAM_REG[39] = 0x090000c8; + DRAM_REG[40] = 0x02008236; + DRAM_REG[41] = 0x0002030a; + DRAM_REG[42] = 0x002d8908; + DRAM_REG[43] = 0x0316050e; + DRAM_REG[44] = 0x02030202; + DRAM_REG[45] = 0x00c80017; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xff000303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x0000050e; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x050e050e; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf5004a27; + DRAM_REG[72] = 0xf5004a27; + DRAM_REG[73] = 0xf5004a27; + DRAM_REG[74] = 0xf5004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000006; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02040303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00050e00; + DRAM_REG[180] = 0x050e050e; + DRAM_REG[181] = 0x04420442; + DRAM_REG[182] = 0x04420442; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} + +void DDR2EmiController_EDE1116_200MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x06005003; + DRAM_REG[39] = 0x0a0000c8; + DRAM_REG[40] = 0x02009c40; + DRAM_REG[41] = 0x0002030c; + DRAM_REG[42] = 0x0036a609; + DRAM_REG[43] = 0x031a0612; + DRAM_REG[44] = 0x02030202; + DRAM_REG[45] = 0x00c8001c; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000612; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x06120612; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf4004a27; + DRAM_REG[72] = 0xf4004a27; + DRAM_REG[73] = 0xf4004a27; + DRAM_REG[74] = 0xf4004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000003; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02040303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00061200; + DRAM_REG[180] = 0x06120612; + DRAM_REG[181] = 0x04420442; + DRAM_REG[182] = 0x04420442; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} +void mDDREmiController_24MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000001; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x05060301; + DRAM_REG[38] = 0x02000001; + DRAM_REG[39] = 0x06000000; + DRAM_REG[40] = 0x020012c0; + DRAM_REG[41] = 0x00020102; + DRAM_REG[42] = 0x00068601; + DRAM_REG[43] = 0x01030055; + DRAM_REG[44] = 0x03010001; + DRAM_REG[45] = 0x00040004; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000055; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x00550055; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf3004925; + DRAM_REG[72] = 0xf3004925; + DRAM_REG[73] = 0xf3004925; + DRAM_REG[74] = 0xf3004925; + DRAM_REG[75] = 0x07400300; + DRAM_REG[76] = 0x07400300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00800004; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x1034a138; + DRAM_REG[88] = 0x1034a138; + DRAM_REG[89] = 0x1034a138; + DRAM_REG[90] = 0x1034a138; + DRAM_REG[91] = 0x00329f53; + DRAM_REG[92] = 0x00329f53; + DRAM_REG[93] = 0x00329f53; + DRAM_REG[94] = 0x00329f53; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00020303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01010101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00005500; + DRAM_REG[180] = 0x00550055; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + +void mDDREmiController_133MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07060301; + DRAM_REG[38] = 0x04000001; + DRAM_REG[39] = 0x0a000000; + DRAM_REG[40] = 0x02000020; + DRAM_REG[41] = 0x00020208; + DRAM_REG[42] = 0x00246c06; + DRAM_REG[43] = 0x020f0200; + DRAM_REG[44] = 0x03020002; + DRAM_REG[45] = 0x00150013; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000200; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x02000200; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf3004b27; + DRAM_REG[72] = 0xf3004b27; + DRAM_REG[73] = 0xf3004b27; + DRAM_REG[74] = 0xf3004b27; + DRAM_REG[75] = 0x07400310; + DRAM_REG[76] = 0x07400310; + DRAM_REG[77] = 0x07400310; + DRAM_REG[78] = 0x07400310; + DRAM_REG[79] = 0x00800004; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00099f36; + DRAM_REG[88] = 0x00099f36; + DRAM_REG[89] = 0x00099f36; + DRAM_REG[90] = 0x00099f36; + DRAM_REG[91] = 0x00091f0f; + DRAM_REG[92] = 0x00091f0f; + DRAM_REG[93] = 0x00091f0f; + DRAM_REG[94] = 0x00091f0f; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01020101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00020000; + DRAM_REG[180] = 0x02000200; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + +void mDDREmiController_200MHz(void) +{ + + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x08060301; + DRAM_REG[38] = 0x06000001; + DRAM_REG[39] = 0x0a000000; + DRAM_REG[40] = 0x02000020; + DRAM_REG[41] = 0x0002030b; + DRAM_REG[42] = 0x0036a608; + DRAM_REG[43] = 0x03160305; + DRAM_REG[44] = 0x03030002; + DRAM_REG[45] = 0x001f001c; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000305; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x03050305; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf4004b27; + DRAM_REG[72] = 0xf4004b27; + DRAM_REG[73] = 0xf4004b27; + DRAM_REG[74] = 0xf4004b27; + DRAM_REG[75] = 0x07000310; + DRAM_REG[76] = 0x07000310; + DRAM_REG[77] = 0x07000310; + DRAM_REG[78] = 0x07000310; + DRAM_REG[79] = 0x00800005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00069f24; + DRAM_REG[88] = 0x00069f24; + DRAM_REG[89] = 0x00069f24; + DRAM_REG[90] = 0x00069f24; + DRAM_REG[91] = 0x00061f0a; + DRAM_REG[92] = 0x00061f0a; + DRAM_REG[93] = 0x00061f0a; + DRAM_REG[94] = 0x00061f0a; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00020303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01030101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00030500; + DRAM_REG[180] = 0x03050305; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + + diff --git a/arch/arm/mach-mx28/emi_settings.h b/arch/arm/mach-mx28/emi_settings.h new file mode 100644 index 000000000000..d22261fc3522 --- /dev/null +++ b/arch/arm/mach-mx28/emi_settings.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _EMI_SETTINGS_H_ +#define _EMI_SETTINGS_H_ + +#define MX28_DRAMCTRLREGNUM 190 + +#define SCALING_DATA_EMI_DIV_OFFSET 0 +#define SCALING_DATA_FRAC_DIV_OFFSET 4 +#define SCALING_DATA_CUR_FREQ_OFFSET 8 +#define SCALING_DATA_NEW_FREQ_OFFSET 12 + +#ifndef __ASSEMBLER__ +void mxs_ram_freq_scale_end(); +void DDR2EmiController_EDE1116_133MHz(void); +void DDR2EmiController_EDE1116_166MHz(void); +void DDR2EmiController_EDE1116_200MHz(void); +void mDDREmiController_24MHz(void); +void mDDREmiController_133MHz(void); +void mDDREmiController_200MHz(void); +unsigned int *get_current_emidata(); +#endif + +#endif diff --git a/arch/arm/mach-mx28/gpio.c b/arch/arm/mach-mx28/gpio.c new file mode 100644 index 000000000000..4f7d42422c78 --- /dev/null +++ b/arch/arm/mach-mx28/gpio.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (input) + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET); + + return 0; +} + +static int mx28_gpio_get(struct mxs_gpio_port *port, int pin) +{ + unsigned int data; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + data = __raw_readl(base + HW_PINCTRL_DIN0); + return data & (1 << pin); +} + +static void mx28_gpio_set(struct mxs_gpio_port *port, int pin, int data) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (data) + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR); +} + +static unsigned int mx28_gpio_irq_stat(struct mxs_gpio_port *port) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + return mask; +} + +static int +mx28_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type) +{ + unsigned int level, pol; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level = 0; + pol = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + level = 0; + pol = 0; + break; + case IRQ_TYPE_LEVEL_HIGH: + level = 1; + pol = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + level = 1; + pol = 0; + break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + + if (level) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR); + + if (pol) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR); + + return 0; +} + +static void mx28_gpio_unmask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET); +} + +static void mx28_gpio_mask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR); +} + +static void mx28_gpio_ack_irq(struct mxs_gpio_port *port, int pin) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = 1 << pin; + if (mask) + __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR); +} + +static struct mxs_gpio_port mx28_gpios[] = { + { + .irq = IRQ_GPIO0, + }, + { + .irq = IRQ_GPIO1, + }, + { + .irq = IRQ_GPIO2, + }, + { + .irq = IRQ_GPIO3, + }, + { + .irq = IRQ_GPIO4, + }, +}; + +static struct mxs_gpio_chip mx28_gpio_chip = { + .set_dir = mx28_gpio_direction, + .get = mx28_gpio_get, + .set = mx28_gpio_set, + .get_irq_stat = mx28_gpio_irq_stat, + .set_irq_type = mx28_gpio_set_irq_type, + .unmask_irq = mx28_gpio_unmask_irq, + .mask_irq = mx28_gpio_mask_irq, + .ack_irq = mx28_gpio_ack_irq, +}; + +int __init mx28_gpio_init(void) +{ + int i; + unsigned int reg; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL); + for (i = 0; i < ARRAY_SIZE(mx28_gpios); i++) { + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i; + if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i))) + continue; + mxs_set_gpio_chip(&mx28_gpios[i], &mx28_gpio_chip); + mx28_gpios[i].id = i; + __raw_writel(0, base + HW_PINCTRL_IRQEN0); + __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0); + mx28_gpios[i].child_irq = MXS_GPIO_IRQ_START + + (i * PINS_PER_BANK); + mxs_add_gpio_port(&mx28_gpios[i]); + } + return 0; +} diff --git a/arch/arm/mach-mx28/include/mach/dma.h b/arch/arm/mach-mx28/include/mach/dma.h new file mode 100644 index 000000000000..ad8076c5d8f3 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_UART4_RX = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_03, + MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_I2C0, + MXS_DMA_CHANNEL_AHB_APBX_I2C1, + MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/lcdif.h b/arch/arm/mach-mx28/include/mach/lcdif.h new file mode 100644 index 000000000000..23fff95968ba --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/lcdif.h @@ -0,0 +1,276 @@ +/* + * Freescale MXS LCDIF interfaces + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include <linux/types.h> +#include <linux/fb.h> +#include <linux/list.h> +#include <linux/backlight.h> +#include <linux/dma-mapping.h> +#include <linux/regulator/consumer.h> +#include <linux/platform_device.h> + +#include <mach/device.h> + +#include "regs-lcdif.h" + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct mxs_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + MXS_LCD_PANEL_SYSTEM = 0, + MXS_LCD_PANEL_VSYNC, + MXS_LCD_PANEL_DOTCLK, + MXS_LCD_PANEL_DVI, +}; + +struct mxs_platform_bl_data; +struct mxs_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device *, dma_addr_t, int, + struct mxs_platform_fb_entry *); + void (*release_panel) (struct device *, struct mxs_platform_fb_entry *); + int (*blank_panel) (int); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t); + int (*update_panel) (void *, struct mxs_platform_fb_entry *); + struct list_head link; + struct mxs_platform_bl_data *bl_data; +}; + +struct mxs_platform_fb_data { + struct list_head list; + struct mxs_platform_fb_entry *cur; + struct mxs_platform_fb_entry *next; +}; + +#define MXS_LCDIF_PANEL_INIT 1 +#define MXS_LCDIF_PANEL_RELEASE 2 + +struct mxs_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct mxs_platform_bl_data *); + int (*set_bl_intensity) (struct mxs_platform_bl_data *, + struct backlight_device *, int); + void (*free_bl) (struct mxs_platform_bl_data *); +}; + +static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_move(&pentry->link, &pdata->list); +} + +static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data + *pdata, + int (*func) (struct + mxs_platform_fb_entry + * pentry, void *data, + int ret_prev), void *data) +{ + struct mxs_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data + *pdata) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-bl", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->dev.platform_data = pdata; +} + +void mxs_init_lcdif(void); +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize); +void mxs_lcdif_dma_release(void); +void mxs_lcdif_run(void); +void mxs_lcdif_stop(void); +int mxs_lcdif_pan_display(dma_addr_t addr); + +int mxs_lcdif_register_client(struct notifier_block *nb); +void mxs_lcdif_unregister_client(struct notifier_block *nb); +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); /* vsync is output */ + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h new file mode 100644 index 000000000000..097253266709 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/mx28.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX28_H__ +#define __ASM_ARCH_MACH_MX28_H__ + +#include <asm/sizes.h> + +#define MX28_SOC_IO_PHYS_BASE 0x80000000 +#define MX28_SOC_IO_VIRT_BASE 0xF0000000 +#define MX28_SOC_IO_AREA_SIZE SZ_1M + +/* Virtual address where OCRAM is mapped */ +#define MX28_OCRAM_PHBASE 0x00000000 +#ifdef __ASSEMBLER__ +#define MX28_OCRAM_BASE 0xf1000000 +#else +#define MX28_OCRAM_BASE (void __iomem *)0xf1000000 +#endif +#define MX28_OCRAM_SIZE (128 * SZ_1K) + + +#define ICOLL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x000000) +#define HSADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x002000) +#define APBH_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x004000) +#define PERFMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x006000) +#define BCH_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x010000) +#define SSP1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x012000) +#define SSP2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x014000) +#define SSP3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x016000) +#define PINCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x022000) +#define APBX_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x030000) +#define CAN0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x032000) +#define CAN1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x034000) +#define SIMDBG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C000) +#define SIMGPMISEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C200) +#define SIMSSPSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C300) +#define SIMMEMSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C400) +#define GPIOMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C500) +#define SIMENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C700) +#define ARMJTAG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C800) +#define CLKCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x046000) +#define LRADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x056000) +#define I2C0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x058000) +#define I2C1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x05A000) +#define PWM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x068000) +#define AUART0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06A000) +#define AUART1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06E000) +#define AUART3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x070000) +#define AUART4_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x072000) +#define DUART_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x074000) +#define USBPHY0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07C000) +#define USBPHY1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07E000) +#define USBCTRL0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x080000) +#define USBCTRL1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x090000) +#define DFLPT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0C0000) +#define DRAM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0E0000) +#define ENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0F0000) + +/* IRQ Definitions */ +#define IRQ_BATT_BRNOUT 0 +#define IRQ_VDDD_BRNOUT 1 +#define IRQ_VDDIO_BRNOUT 2 +#define IRQ_VDDA_BRNOUT 3 +#define IRQ_VDD5V_DROOP 4 +#define IRQ_DCDC4P2_BRNOUT 5 +#define IRQ_VDD5V 6 +#define IRQ_RESV7 7 +#define IRQ_CAN0 8 +#define IRQ_CAN1 9 +#define IRQ_LRADC_TOUCH 10 +#define IRQ_RESV11 11 +#define IRQ_RESV12 12 +#define IRQ_HSADC 13 +#define IRQ_IRADC_THRESH0 14 +#define IRQ_IRADC_THRESH1 15 +#define IRQ_LRADC_CH0 16 +#define IRQ_LRADC_CH1 17 +#define IRQ_LRADC_CH2 18 +#define IRQ_LRADC_CH3 19 +#define IRQ_LRADC_CH4 20 +#define IRQ_LRADC_CH5 21 +#define IRQ_LRADC_CH6 22 +#define IRQ_LRADC_CH7 23 +#define IRQ_LRADC_BUTTON0 24 +#define IRQ_LRADC_BUTTON1 25 +#define IRQ_RESV26 26 +#define IRQ_PERFMON 27 +#define IRQ_RTC_1MSEC 28 +#define IRQ_RTC_ALARM 29 +#define IRQ_RESV30 30 +#define IRQ_COMMS 31 +#define IRQ_EMI_ERR 32 +#define IRQ_RESV33 33 +#define IRQ_RESV34 34 +#define IRQ_RESV35 35 +#define IRQ_RESV36 36 +#define IRQ_RESV37 37 +#define IRQ_LCDIF 38 +#define IRQ_PXP 39 +#define IRQ_RESV40 40 +#define IRQ_BCH 41 +#define IRQ_GPMI 42 +#define IRQ_RESV43 43 +#define IRQ_RESV44 44 +#define IRQ_SPDIF_ERROR 45 +#define IRQ_RESV46 46 +#define IRQ_DUART 47 +#define IRQ_TIMER0 48 +#define IRQ_TIMER1 49 +#define IRQ_TIMER2 50 +#define IRQ_TIMER3 51 +#define IRQ_DCP_VMI 52 +#define IRQ_DCP 53 +#define IRQ_DCP_SECURE 54 +#define IRQ_RESV55 55 +#define IRQ_RESV56 56 +#define IRQ_RESV57 57 +#define IRQ_SAIF1 58 +#define IRQ_SAIF0 59 +#define IRQ_RESV60 60 +#define IRQ_RESV61 61 +#define IRQ_RESV62 62 +#define IRQ_RESV63 63 +#define IRQ_RESV64 64 +#define IRQ_RESV65 65 +#define IRQ_SPDIF_DMA 66 +#define IRQ_RESV67 67 +#define IRQ_I2C0_DMA 68 +#define IRQ_I2C1_DMA 69 +#define IRQ_AUART0_RX_DMA 70 +#define IRQ_AUART0_TX_DMA 71 +#define IRQ_AUART1_RX_DMA 72 +#define IRQ_AUART1_TX_DMA 73 +#define IRQ_AUART2_RX_DMA 74 +#define IRQ_AUART2_TX_DMA 75 +#define IRQ_AUART3_RX_DMA 76 +#define IRQ_AUART3_TX_DMA 77 +#define IRQ_AUART4_RX_DMA 78 +#define IRQ_AUART4_TX_DMA 79 +#define IRQ_SAIF0_DMA 80 +#define IRQ_SAIF1_DMA 81 +#define IRQ_SSP0_DMA 82 +#define IRQ_SSP1_DMA 83 +#define IRQ_SSP2_DMA 84 +#define IRQ_SSP3_DMA 85 +#define IRQ_LCDIF_DMA 86 +#define IRQ_HSADC_DMA 87 +#define IRQ_GPMI_DMA 88 +#define IRQ_DIGCTL_DEBUG_TRAP 89 +#define IRQ_RESV90 90 +#define IRQ_RESV91 91 +#define IRQ_USB1 92 +#define IRQ_USB0 93 +#define IRQ_USB1_WAKEUP 94 +#define IRQ_USB0_WAKEUP 95 +#define IRQ_SSP0 96 +#define IRQ_SSP1 97 +#define IRQ_SSP2 98 +#define IRQ_SSP3 99 +#define IRQ_ENET_SWI 100 +#define IRQ_ENET_MAC0 101 +#define IRQ_ENET_MAC1 102 +#define IRQ_ENET_MAC0_1588 103 +#define IRQ_ENET_MAC1_1588 104 +#define IRQ_RESV105 105 +#define IRQ_RESV106 106 +#define IRQ_RESV107 107 +#define IRQ_RESV108 108 +#define IRQ_RESV109 109 +#define IRQ_I2C1_ERROR 110 +#define IRQ_I2C0_ERROR 111 +#define IRQ_AUART0 112 +#define IRQ_AUART1 113 +#define IRQ_AUART2 114 +#define IRQ_AUART3 115 +#define IRQ_AUART4 116 +#define IRQ_RESV117 117 +#define IRQ_RESV118 118 +#define IRQ_RESV119 119 +#define IRQ_RESV120 120 +#define IRQ_RESV121 121 +#define IRQ_RESV122 122 +#define IRQ_GPIO4 123 +#define IRQ_GPIO3 124 +#define IRQ_GPIO2 125 +#define IRQ_GPIO1 126 +#define IRQ_GPIO0 127 + +#define ARCH_NR_IRQS 128 + +/* On i.MX28, all interrupt sources can be configured as FIQ */ +#define FIQ_START IRQ_BATT_BRNOUT + +#define MX28_SOC_IO_ADDRESS(x) \ + ((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE) + +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX28_SOC_IO_ADDRESS(x) +#else +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \ + MX28_SOC_IO_AREA_SIZE) ? \ + MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/regs-apbh.h b/arch/arm/mach-mx28/include/mach/regs-apbh.h new file mode 100644 index 000000000000..23f26ca10e9e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-apbh.h @@ -0,0 +1,535 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2 + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-i2c.h b/arch/arm/mach-mx28/include/mach/regs-i2c.h new file mode 100644 index 000000000000..71997445f44e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-i2c.h @@ -0,0 +1,498 @@ +/* + * Freescale I2C Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.54 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H + + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) + +#define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD2 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_RSVD1 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) + +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) + +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) + +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) + +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) + +#define BM_I2C_CTRL1_RSVD1 0x80000000 +#define BM_I2C_CTRL1_RD_QUEUE_IRQ 0x40000000 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_WR_QUEUE_IRQ 0x20000000 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_QUEUECTRL (0x00000060) +#define HW_I2C_QUEUECTRL_SET (0x00000064) +#define HW_I2C_QUEUECTRL_CLR (0x00000068) +#define HW_I2C_QUEUECTRL_TOG (0x0000006c) + +#define BP_I2C_QUEUECTRL_RSVD3 21 +#define BM_I2C_QUEUECTRL_RSVD3 0xFFE00000 +#define BF_I2C_QUEUECTRL_RSVD3(v) \ + (((v) << 21) & BM_I2C_QUEUECTRL_RSVD3) +#define BP_I2C_QUEUECTRL_RD_THRESH 16 +#define BM_I2C_QUEUECTRL_RD_THRESH 0x001F0000 +#define BF_I2C_QUEUECTRL_RD_THRESH(v) \ + (((v) << 16) & BM_I2C_QUEUECTRL_RD_THRESH) +#define BP_I2C_QUEUECTRL_RSVD2 13 +#define BM_I2C_QUEUECTRL_RSVD2 0x0000E000 +#define BF_I2C_QUEUECTRL_RSVD2(v) \ + (((v) << 13) & BM_I2C_QUEUECTRL_RSVD2) +#define BP_I2C_QUEUECTRL_WR_THRESH 8 +#define BM_I2C_QUEUECTRL_WR_THRESH 0x00001F00 +#define BF_I2C_QUEUECTRL_WR_THRESH(v) \ + (((v) << 8) & BM_I2C_QUEUECTRL_WR_THRESH) +#define BP_I2C_QUEUECTRL_RSVD1 6 +#define BM_I2C_QUEUECTRL_RSVD1 0x000000C0 +#define BF_I2C_QUEUECTRL_RSVD1(v) \ + (((v) << 6) & BM_I2C_QUEUECTRL_RSVD1) +#define BM_I2C_QUEUECTRL_QUEUE_RUN 0x00000020 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__STOP 0x0 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__START 0x1 +#define BM_I2C_QUEUECTRL_RD_CLEAR 0x00000010 +#define BM_I2C_QUEUECTRL_WR_CLEAR 0x00000008 +#define BM_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x00000004 +#define BM_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN 0x00000002 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN 0x00000001 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__ENABLED 0x1 + +#define HW_I2C_QUEUESTAT (0x00000070) +#define HW_I2C_QUEUESTAT_SET (0x00000074) +#define HW_I2C_QUEUESTAT_CLR (0x00000078) +#define HW_I2C_QUEUESTAT_TOG (0x0000007c) + +#define BP_I2C_QUEUESTAT_RSVD2 15 +#define BM_I2C_QUEUESTAT_RSVD2 0xFFFF8000 +#define BF_I2C_QUEUESTAT_RSVD2(v) \ + (((v) << 15) & BM_I2C_QUEUESTAT_RSVD2) +#define BM_I2C_QUEUESTAT_RD_QUEUE_FULL 0x00004000 +#define BM_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 +#define BP_I2C_QUEUESTAT_RD_QUEUE_CNT 8 +#define BM_I2C_QUEUESTAT_RD_QUEUE_CNT 0x00001F00 +#define BF_I2C_QUEUESTAT_RD_QUEUE_CNT(v) \ + (((v) << 8) & BM_I2C_QUEUESTAT_RD_QUEUE_CNT) +#define BM_I2C_QUEUESTAT_RSVD1 0x00000080 +#define BM_I2C_QUEUESTAT_WR_QUEUE_FULL 0x00000040 +#define BM_I2C_QUEUESTAT_WR_QUEUE_EMPTY 0x00000020 +#define BP_I2C_QUEUESTAT_WR_QUEUE_CNT 0 +#define BM_I2C_QUEUESTAT_WR_QUEUE_CNT 0x0000001F +#define BF_I2C_QUEUESTAT_WR_QUEUE_CNT(v) \ + (((v) << 0) & BM_I2C_QUEUESTAT_WR_QUEUE_CNT) + +#define HW_I2C_QUEUECMD (0x00000080) +#define HW_I2C_QUEUECMD_SET (0x00000084) +#define HW_I2C_QUEUECMD_CLR (0x00000088) +#define HW_I2C_QUEUECMD_TOG (0x0000008c) + +#define BP_I2C_QUEUECMD_RSVD2 28 +#define BM_I2C_QUEUECMD_RSVD2 0xF0000000 +#define BF_I2C_QUEUECMD_RSVD2(v) \ + (((v) << 28) & BM_I2C_QUEUECMD_RSVD2) +#define BM_I2C_QUEUECMD_PRE_ACK 0x08000000 +#define BM_I2C_QUEUECMD_ACKNOWLEDGE 0x04000000 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_QUEUECMD_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_QUEUECMD_RSVD1 0x01000000 +#define BM_I2C_QUEUECMD_MULTI_MASTER 0x00800000 +#define BV_I2C_QUEUECMD_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_QUEUECMD_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_QUEUECMD_CLOCK_HELD 0x00400000 +#define BV_I2C_QUEUECMD_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_QUEUECMD_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_QUEUECMD_RETAIN_CLOCK 0x00200000 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_QUEUECMD_POST_SEND_STOP 0x00100000 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_QUEUECMD_PRE_SEND_START 0x00080000 +#define BV_I2C_QUEUECMD_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_QUEUECMD_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_QUEUECMD_MASTER_MODE 0x00020000 +#define BV_I2C_QUEUECMD_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_QUEUECMD_MASTER_MODE__MASTER 0x1 +#define BM_I2C_QUEUECMD_DIRECTION 0x00010000 +#define BV_I2C_QUEUECMD_DIRECTION__RECEIVE 0x0 +#define BV_I2C_QUEUECMD_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_QUEUECMD_XFER_COUNT 0 +#define BM_I2C_QUEUECMD_XFER_COUNT 0x0000FFFF +#define BF_I2C_QUEUECMD_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_QUEUECMD_XFER_COUNT) + +#define HW_I2C_QUEUEDATA (0x00000090) + +#define BP_I2C_QUEUEDATA_DATA 0 +#define BM_I2C_QUEUEDATA_DATA 0xFFFFFFFF +#define BF_I2C_QUEUEDATA_DATA(v) (v) + +#define HW_I2C_DATA (0x000000a0) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x000000b0) +#define HW_I2C_DEBUG0_SET (0x000000b4) +#define HW_I2C_DEBUG0_CLR (0x000000b8) +#define HW_I2C_DEBUG0_TOG (0x000000bc) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_STATE_VALUE 26 +#define BM_I2C_DEBUG0_STATE_VALUE 0x0C000000 +#define BF_I2C_DEBUG0_STATE_VALUE(v) \ + (((v) << 26) & BM_I2C_DEBUG0_STATE_VALUE) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_STATE_LATCH 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x000000c0) +#define HW_I2C_DEBUG1_SET (0x000000c4) +#define HW_I2C_DEBUG1_CLR (0x000000c8) +#define HW_I2C_DEBUG1_TOG (0x000000cc) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x000000d0) + +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-icoll.h b/arch/arm/mach-mx28/include/mach/regs-icoll.h new file mode 100644 index 000000000000..f06ac0d4720b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-icoll.h @@ -0,0 +1,293 @@ +/* + * Freescale ICOLL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H + +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) + +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) + +#define HW_ICOLL_STAT (0x00000070) + +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) + +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) + +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lcdif.h b/arch/arm/mach-mx28/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..6a0e008be308 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lcdif.h @@ -0,0 +1,680 @@ +/* + * Freescale LCDIF Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H + + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) + +#define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_READ_WRITEB 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_RSRVD0 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 + +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) + +#define BP_LCDIF_CTRL1_RSRVD1 28 +#define BM_LCDIF_CTRL1_RSRVD1 0xF0000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_COMBINE_MPU_WR_STRB 0x08000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BP_LCDIF_CTRL1_RSRVD0 3 +#define BM_LCDIF_CTRL1_RSRVD0 0x000000F8 +#define BF_LCDIF_CTRL1_RSRVD0(v) \ + (((v) << 3) & BM_LCDIF_CTRL1_RSRVD0) +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_CTRL2 (0x00000020) +#define HW_LCDIF_CTRL2_SET (0x00000024) +#define HW_LCDIF_CTRL2_CLR (0x00000028) +#define HW_LCDIF_CTRL2_TOG (0x0000002c) + +#define BP_LCDIF_CTRL2_RSRVD5 24 +#define BM_LCDIF_CTRL2_RSRVD5 0xFF000000 +#define BF_LCDIF_CTRL2_RSRVD5(v) \ + (((v) << 24) & BM_LCDIF_CTRL2_RSRVD5) +#define BP_LCDIF_CTRL2_OUTSTANDING_REQS 21 +#define BM_LCDIF_CTRL2_OUTSTANDING_REQS 0x00E00000 +#define BF_LCDIF_CTRL2_OUTSTANDING_REQS(v) \ + (((v) << 21) & BM_LCDIF_CTRL2_OUTSTANDING_REQS) +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_1 0x0 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_2 0x1 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_4 0x2 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_8 0x3 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4 +#define BM_LCDIF_CTRL2_BURST_LEN_8 0x00100000 +#define BM_LCDIF_CTRL2_RSRVD4 0x00080000 +#define BP_LCDIF_CTRL2_ODD_LINE_PATTERN 16 +#define BM_LCDIF_CTRL2_ODD_LINE_PATTERN 0x00070000 +#define BF_LCDIF_CTRL2_ODD_LINE_PATTERN(v) \ + (((v) << 16) & BM_LCDIF_CTRL2_ODD_LINE_PATTERN) +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD3 0x00008000 +#define BP_LCDIF_CTRL2_EVEN_LINE_PATTERN 12 +#define BM_LCDIF_CTRL2_EVEN_LINE_PATTERN 0x00007000 +#define BF_LCDIF_CTRL2_EVEN_LINE_PATTERN(v) \ + (((v) << 12) & BM_LCDIF_CTRL2_EVEN_LINE_PATTERN) +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD2 0x00000800 +#define BM_LCDIF_CTRL2_READ_PACK_DIR 0x00000400 +#define BM_LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT 0x00000200 +#define BM_LCDIF_CTRL2_READ_MODE_6_BIT_INPUT 0x00000100 +#define BM_LCDIF_CTRL2_RSRVD1 0x00000080 +#define BP_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 4 +#define BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 0x00000070 +#define BF_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v) \ + (((v) << 4) & BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS) +#define BP_LCDIF_CTRL2_INITIAL_DUMMY_READ 1 +#define BM_LCDIF_CTRL2_INITIAL_DUMMY_READ 0x0000000E +#define BF_LCDIF_CTRL2_INITIAL_DUMMY_READ(v) \ + (((v) << 1) & BM_LCDIF_CTRL2_INITIAL_DUMMY_READ) +#define BM_LCDIF_CTRL2_RSRVD0 0x00000001 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000030) + +#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_LCDIF_CUR_BUF (0x00000040) + +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_LCDIF_NEXT_BUF (0x00000050) + +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_TIMING (0x00000060) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) +#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) + +#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) + +#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 18 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFFFC0000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_LCDIF_VDCTRL3 (0x000000a0) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_LCDIF_VDCTRL4 (0x000000b0) + +#define BP_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 29 +#define BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 0xE0000000 +#define BF_LCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \ + (((v) << 29) & BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL) +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0x1FF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) +#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_LCDIF_DVICTRL0 (0x000000c0) + +#define BP_LCDIF_DVICTRL0_RSRVD1 28 +#define BM_LCDIF_DVICTRL0_RSRVD1 0xF0000000 +#define BF_LCDIF_DVICTRL0_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_DVICTRL0_RSRVD1) +#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 16 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x0FFF0000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_RSRVD0 12 +#define BM_LCDIF_DVICTRL0_RSRVD0 0x0000F000 +#define BF_LCDIF_DVICTRL0_RSRVD0(v) \ + (((v) << 12) & BM_LCDIF_DVICTRL0_RSRVD0) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 0 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x00000FFF +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) + +#define HW_LCDIF_DVICTRL1 (0x000000d0) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) +#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) + +#define HW_LCDIF_DVICTRL2 (0x000000e0) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) +#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL3 (0x000000f0) + +#define BP_LCDIF_DVICTRL3_RSRVD0 30 +#define BM_LCDIF_DVICTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 20 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 10 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) +#define BP_LCDIF_DVICTRL3_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL3_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL3_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V_LINES_CNT) + +#define HW_LCDIF_DVICTRL4 (0x00000100) + +#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_LCDIF_CSC_COEFF0 (0x00000110) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) +#define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_LCDIF_CSC_COEFF1 (0x00000120) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) +#define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) + +#define HW_LCDIF_CSC_COEFF2 (0x00000130) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) +#define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) + +#define HW_LCDIF_CSC_COEFF3 (0x00000140) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) +#define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) + +#define HW_LCDIF_CSC_COEFF4 (0x00000150) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) +#define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) + +#define HW_LCDIF_CSC_OFFSET (0x00000160) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) +#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) + +#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_DATA (0x00000180) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x00000190) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_CRC_STAT (0x000001a0) + +#define BP_LCDIF_CRC_STAT_CRC_VALUE 0 +#define BM_LCDIF_CRC_STAT_CRC_VALUE 0xFFFFFFFF +#define BF_LCDIF_CRC_STAT_CRC_VALUE(v) (v) + +#define HW_LCDIF_STAT (0x000001b0) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 9 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFE00 +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_STAT_RSRVD0) +#define BP_LCDIF_STAT_LFIFO_COUNT 0 +#define BM_LCDIF_STAT_LFIFO_COUNT 0x000001FF +#define BF_LCDIF_STAT_LFIFO_COUNT(v) \ + (((v) << 0) & BM_LCDIF_STAT_LFIFO_COUNT) + +#define HW_LCDIF_VERSION (0x000001c0) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001d0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BP_LCDIF_DEBUG0_CUR_REQ_STATE 10 +#define BM_LCDIF_DEBUG0_CUR_REQ_STATE 0x00000C00 +#define BF_LCDIF_DEBUG0_CUR_REQ_STATE(v) \ + (((v) << 10) & BM_LCDIF_DEBUG0_CUR_REQ_STATE) +#define BM_LCDIF_DEBUG0_MST_AVALID 0x00000200 +#define BP_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 4 +#define BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 0x000001F0 +#define BF_LCDIF_DEBUG0_MST_OUTSTANDING_REQS(v) \ + (((v) << 4) & BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS) +#define BP_LCDIF_DEBUG0_MST_WORDS 0 +#define BM_LCDIF_DEBUG0_MST_WORDS 0x0000000F +#define BF_LCDIF_DEBUG0_MST_WORDS(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_MST_WORDS) + +#define HW_LCDIF_DEBUG1 (0x000001e0) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) + +#define HW_LCDIF_DEBUG2 (0x000001f0) + +#define BP_LCDIF_DEBUG2_MST_ADDRESS 0 +#define BM_LCDIF_DEBUG2_MST_ADDRESS 0xFFFFFFFF +#define BF_LCDIF_DEBUG2_MST_ADDRESS(v) (v) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lradc.h b/arch/arm/mach-mx28/include/mach/regs-lradc.h new file mode 100644 index 000000000000..d7906b91c72e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lradc.h @@ -0,0 +1,772 @@ +/* + * Freescale LRADC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H + + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) + +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 27 +#define BM_LRADC_CTRL0_RSRVD2 0x38000000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 27) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x04000000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON1_DETECT_ENABLE 0x02000000 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON0_DETECT_ENABLE 0x01000000 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00800000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_SCREEN_TYPE 0x00400000 +#define BM_LRADC_CTRL0_YNLRSW 0x00200000 +#define BP_LRADC_CTRL0_YPLLSW 19 +#define BM_LRADC_CTRL0_YPLLSW 0x00180000 +#define BF_LRADC_CTRL0_YPLLSW(v) \ + (((v) << 19) & BM_LRADC_CTRL0_YPLLSW) +#define BP_LRADC_CTRL0_XNURSW 17 +#define BM_LRADC_CTRL0_XNURSW 0x00060000 +#define BF_LRADC_CTRL0_XNURSW(v) \ + (((v) << 17) & BM_LRADC_CTRL0_XNURSW) +#define BM_LRADC_CTRL0_XPULSW 0x00010000 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) + +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) + +#define BP_LRADC_CTRL1_RSRVD2 29 +#define BM_LRADC_CTRL1_RSRVD2 0xE0000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 29) & BM_LRADC_CTRL1_RSRVD2) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN 0x10000000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN 0x08000000 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN 0x04000000 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN 0x02000000 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 13 +#define BM_LRADC_CTRL1_RSRVD1 0x0000E000 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 13) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ 0x00001000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ 0x00000800 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ 0x00000400 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ 0x00000200 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) + +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BP_LRADC_CTRL2_RSRVD3 16 +#define BM_LRADC_CTRL2_RSRVD3 0x00FF0000 +#define BF_LRADC_CTRL2_RSRVD3(v) \ + (((v) << 16) & BM_LRADC_CTRL2_RSRVD3) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BP_LRADC_CTRL2_VTHSENSE 13 +#define BM_LRADC_CTRL2_VTHSENSE 0x00006000 +#define BF_LRADC_CTRL2_VTHSENSE(v) \ + (((v) << 13) & BM_LRADC_CTRL2_VTHSENSE) +#define BM_LRADC_CTRL2_DISABLE_MUXAMP_BYPASS 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 + +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 + +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) + +#define BP_LRADC_STATUS_RSRVD3 29 +#define BM_LRADC_STATUS_RSRVD3 0xE0000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 29) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_BUTTON1_PRESENT 0x10000000 +#define BM_LRADC_STATUS_BUTTON0_PRESENT 0x08000000 +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 3 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFF8 +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 3) & BM_LRADC_STATUS_RSRVD2) +#define BM_LRADC_STATUS_BUTTON1_DETECT_RAW 0x00000004 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_BUTTON0_DETECT_RAW 0x00000002 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) + +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) + +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) + +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_THRESHOLD0 (0x00000150) +#define HW_LRADC_THRESHOLD0_SET (0x00000154) +#define HW_LRADC_THRESHOLD0_CLR (0x00000158) +#define HW_LRADC_THRESHOLD0_TOG (0x0000015c) + +#define BP_LRADC_THRESHOLD0_RSRVD1 25 +#define BM_LRADC_THRESHOLD0_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD0_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD0_RSRVD1) +#define BM_LRADC_THRESHOLD0_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD0_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD0_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD0_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD0_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD0_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD0_SETTING 18 +#define BM_LRADC_THRESHOLD0_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD0_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD0_SETTING) +#define BV_LRADC_THRESHOLD0_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD0_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD0_VALUE 0 +#define BM_LRADC_THRESHOLD0_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD0_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD0_VALUE) + +#define HW_LRADC_THRESHOLD1 (0x00000160) +#define HW_LRADC_THRESHOLD1_SET (0x00000164) +#define HW_LRADC_THRESHOLD1_CLR (0x00000168) +#define HW_LRADC_THRESHOLD1_TOG (0x0000016c) + +#define BP_LRADC_THRESHOLD1_RSRVD1 25 +#define BM_LRADC_THRESHOLD1_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD1_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD1_RSRVD1) +#define BM_LRADC_THRESHOLD1_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD1_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD1_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD1_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD1_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD1_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD1_SETTING 18 +#define BM_LRADC_THRESHOLD1_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD1_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD1_SETTING) +#define BV_LRADC_THRESHOLD1_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD1_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD1_VALUE 0 +#define BM_LRADC_THRESHOLD1_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD1_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD1_VALUE) + +#define HW_LRADC_VERSION (0x00000170) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ocotp.h b/arch/arm/mach-mx28/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..7907250116ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ocotp.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BP_OCOTP_CUSTCAP_RSRVD1 3 +#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BM_OCOTP_LOCK_SRK 0x00008000 +#define BP_OCOTP_LOCK_UNALLOCATED 12 +#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_ROMn + * base 0x000001A0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10) +#define BP_OCOTP_ROMn_BOOT_MODE 24 +#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROMn_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE) +#define BP_OCOTP_ROMn_SD_MMC_MODE 22 +#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000 +#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \ + (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE) +#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH) +#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX) +#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080 +#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040 +#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010 +#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROMn_RSRVD2 0x00000004 +#define BM_OCOTP_ROMn_RSRVD1 0x00000002 +#define BM_OCOTP_ROMn_RSRVD0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x00000220 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x000002a0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-power.h b/arch/arm/mach-mx28/include/mach/regs-power.h new file mode 100644 index 000000000000..8f6a8eeefa4b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-power.h @@ -0,0 +1,683 @@ +/* + * Freescale POWER Register Definitions + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H + + +#include <mach/mx28.h> + +#define REGS_POWER_BASE IO_ADDRESS(POWER_PHYS_ADDR) +#define REGS_POWER_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 + +#define HW_POWER_CTRL (0x00000000) +#define HW_POWER_CTRL_SET (0x00000004) +#define HW_POWER_CTRL_CLR (0x00000008) +#define HW_POWER_CTRL_TOG (0x0000000c) + +#define BP_POWER_CTRL_RSRVD2 28 +#define BM_POWER_CTRL_RSRVD2 0xF0000000 +#define BF_POWER_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_POWER_CTRL_RSRVD2) +#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000 +#define BP_POWER_CTRL_RSRVD1 25 +#define BM_POWER_CTRL_RSRVD1 0x06000000 +#define BF_POWER_CTRL_RSRVD1(v) \ + (((v) << 25) & BM_POWER_CTRL_RSRVD1) +#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000 +#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000 +#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000 +#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 +#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000 +#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 + +#define HW_POWER_5VCTRL (0x00000010) +#define HW_POWER_5VCTRL_SET (0x00000014) +#define HW_POWER_5VCTRL_CLR (0x00000018) +#define HW_POWER_5VCTRL_TOG (0x0000001c) + +#define BP_POWER_5VCTRL_RSRVD6 30 +#define BM_POWER_5VCTRL_RSRVD6 0xC0000000 +#define BF_POWER_5VCTRL_RSRVD6(v) \ + (((v) << 30) & BM_POWER_5VCTRL_RSRVD6) +#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 +#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 +#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \ + (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH) +#define BM_POWER_5VCTRL_RSRVD5 0x08000000 +#define BP_POWER_5VCTRL_HEADROOM_ADJ 24 +#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000 +#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \ + (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ) +#define BP_POWER_5VCTRL_RSRVD4 22 +#define BM_POWER_5VCTRL_RSRVD4 0x00C00000 +#define BF_POWER_5VCTRL_RSRVD4(v) \ + (((v) << 22) & BM_POWER_5VCTRL_RSRVD4) +#define BP_POWER_5VCTRL_PWD_CHARGE_4P2 20 +#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00300000 +#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v) \ + (((v) << 20) & BM_POWER_5VCTRL_PWD_CHARGE_4P2) +#define BP_POWER_5VCTRL_RSRVD3 18 +#define BM_POWER_5VCTRL_RSRVD3 0x000C0000 +#define BF_POWER_5VCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_5VCTRL_RSRVD3) +#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 +#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000 +#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \ + (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) +#define BM_POWER_5VCTRL_RSRVD2 0x00000800 +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \ + (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH) +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080 +#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 +#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004 +#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001 + +#define HW_POWER_MINPWR (0x00000020) +#define HW_POWER_MINPWR_SET (0x00000024) +#define HW_POWER_MINPWR_CLR (0x00000028) +#define HW_POWER_MINPWR_TOG (0x0000002c) + +#define BP_POWER_MINPWR_RSRVD1 15 +#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000 +#define BF_POWER_MINPWR_RSRVD1(v) \ + (((v) << 15) & BM_POWER_MINPWR_RSRVD1) +#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000 +#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000 +#define BM_POWER_MINPWR_PWD_BO 0x00001000 +#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800 +#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400 +#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200 +#define BM_POWER_MINPWR_SELECT_OSC 0x00000100 +#define BM_POWER_MINPWR_VBG_OFF 0x00000080 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040 +#define BM_POWER_MINPWR_HALF_FETS 0x00000020 +#define BM_POWER_MINPWR_LESSANA_I 0x00000010 +#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008 +#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004 +#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002 +#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001 + +#define HW_POWER_CHARGE (0x00000030) +#define HW_POWER_CHARGE_SET (0x00000034) +#define HW_POWER_CHARGE_CLR (0x00000038) +#define HW_POWER_CHARGE_TOG (0x0000003c) + +#define BP_POWER_CHARGE_RSRVD6 27 +#define BM_POWER_CHARGE_RSRVD6 0xF8000000 +#define BF_POWER_CHARGE_RSRVD6(v) \ + (((v) << 27) & BM_POWER_CHARGE_RSRVD6) +#define BP_POWER_CHARGE_ADJ_VOLT 24 +#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000 +#define BF_POWER_CHARGE_ADJ_VOLT(v) \ + (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT) +#define BM_POWER_CHARGE_RSRVD5 0x00800000 +#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000 +#define BM_POWER_CHARGE_RSRVD4 0x00200000 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000 +#define BM_POWER_CHARGE_LIION_4P1 0x00040000 +#define BM_POWER_CHARGE_RSRVD3 0x00020000 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000 +#define BP_POWER_CHARGE_RSRVD2 14 +#define BM_POWER_CHARGE_RSRVD2 0x0000C000 +#define BF_POWER_CHARGE_RSRVD2(v) \ + (((v) << 14) & BM_POWER_CHARGE_RSRVD2) +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB1 0x00002000 +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB0 0x00001000 +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) \ + (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT) +#define BP_POWER_CHARGE_RSRVD1 6 +#define BM_POWER_CHARGE_RSRVD1 0x000000C0 +#define BF_POWER_CHARGE_RSRVD1(v) \ + (((v) << 6) & BM_POWER_CHARGE_RSRVD1) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F +#define BF_POWER_CHARGE_BATTCHRG_I(v) \ + (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I) + +#define HW_POWER_VDDDCTRL (0x00000040) + +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) \ + (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN) +#define BP_POWER_VDDDCTRL_RSRVD4 24 +#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000 +#define BF_POWER_VDDDCTRL_RSRVD4(v) \ + (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4) +#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000 +#define BP_POWER_VDDDCTRL_RSRVD3 18 +#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000 +#define BF_POWER_VDDDCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \ + (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD2 11 +#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800 +#define BF_POWER_VDDDCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD1 5 +#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDDCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x0000001F +#define BF_POWER_VDDDCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDDCTRL_TRG) + +#define HW_POWER_VDDACTRL (0x00000050) + +#define BP_POWER_VDDACTRL_RSRVD4 20 +#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000 +#define BF_POWER_VDDACTRL_RSRVD4(v) \ + (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4) +#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDACTRL_RSRVD3 14 +#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDACTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET) +#define BM_POWER_VDDACTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET) +#define BP_POWER_VDDACTRL_RSRVD1 5 +#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDACTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x0000001F +#define BF_POWER_VDDACTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDACTRL_TRG) + +#define HW_POWER_VDDIOCTRL (0x00000060) + +#define BP_POWER_VDDIOCTRL_RSRVD5 24 +#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000 +#define BF_POWER_VDDIOCTRL_RSRVD5(v) \ + (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5) +#define BP_POWER_VDDIOCTRL_ADJTN 20 +#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) \ + (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN) +#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000 +#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDIOCTRL_RSRVD3 14 +#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDIOCTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET) +#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET) +#define BP_POWER_VDDIOCTRL_RSRVD1 5 +#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDIOCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1) +#define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define BF_POWER_VDDIOCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDIOCTRL_TRG) + +#define HW_POWER_VDDMEMCTRL (0x00000070) + +#define BP_POWER_VDDMEMCTRL_RSRVD2 11 +#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800 +#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2) +#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400 +#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200 +#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100 +#define BP_POWER_VDDMEMCTRL_BO_OFFSET 5 +#define BM_POWER_VDDMEMCTRL_BO_OFFSET 0x000000E0 +#define BF_POWER_VDDMEMCTRL_BO_OFFSET(v) \ + (((v) << 5) & BM_POWER_VDDMEMCTRL_BO_OFFSET) +#define BP_POWER_VDDMEMCTRL_TRG 0 +#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F +#define BF_POWER_VDDMEMCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG) + +#define HW_POWER_DCDC4P2 (0x00000080) + +#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 +#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000 +#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \ + (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL) +#define BP_POWER_DCDC4P2_RSRVD5 26 +#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000 +#define BF_POWER_DCDC4P2_RSRVD5(v) \ + (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5) +#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 +#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000 +#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \ + (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH) +#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000 +#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000 +#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000 +#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000 +#define BM_POWER_DCDC4P2_RSRVD3 0x00080000 +#define BP_POWER_DCDC4P2_TRG 16 +#define BM_POWER_DCDC4P2_TRG 0x00070000 +#define BF_POWER_DCDC4P2_TRG(v) \ + (((v) << 16) & BM_POWER_DCDC4P2_TRG) +#define BP_POWER_DCDC4P2_RSRVD2 13 +#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000 +#define BF_POWER_DCDC4P2_RSRVD2(v) \ + (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2) +#define BP_POWER_DCDC4P2_BO 8 +#define BM_POWER_DCDC4P2_BO 0x00001F00 +#define BF_POWER_DCDC4P2_BO(v) \ + (((v) << 8) & BM_POWER_DCDC4P2_BO) +#define BP_POWER_DCDC4P2_RSRVD1 5 +#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0 +#define BF_POWER_DCDC4P2_RSRVD1(v) \ + (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1) +#define BP_POWER_DCDC4P2_CMPTRIP 0 +#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F +#define BF_POWER_DCDC4P2_CMPTRIP(v) \ + (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP) + +#define HW_POWER_MISC (0x00000090) + +#define BP_POWER_MISC_RSRVD2 7 +#define BM_POWER_MISC_RSRVD2 0xFFFFFF80 +#define BF_POWER_MISC_RSRVD2(v) \ + (((v) << 7) & BM_POWER_MISC_RSRVD2) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x00000070 +#define BF_POWER_MISC_FREQSEL(v) \ + (((v) << 4) & BM_POWER_MISC_FREQSEL) +#define BM_POWER_MISC_DISABLEFET_BO_LOGIC 0x00000008 +#define BM_POWER_MISC_DELAY_TIMING 0x00000004 +#define BM_POWER_MISC_TEST 0x00000002 +#define BM_POWER_MISC_SEL_PLLCLK 0x00000001 + +#define HW_POWER_DCLIMITS (0x000000a0) + +#define BP_POWER_DCLIMITS_RSRVD3 16 +#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000 +#define BF_POWER_DCLIMITS_RSRVD3(v) \ + (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3) +#define BM_POWER_DCLIMITS_RSRVD2 0x00008000 +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \ + (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK) +#define BM_POWER_DCLIMITS_RSRVD1 0x00000080 +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F +#define BF_POWER_DCLIMITS_NEGLIMIT(v) \ + (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT) + +#define HW_POWER_LOOPCTRL (0x000000b0) +#define HW_POWER_LOOPCTRL_SET (0x000000b4) +#define HW_POWER_LOOPCTRL_CLR (0x000000b8) +#define HW_POWER_LOOPCTRL_TOG (0x000000bc) + +#define BP_POWER_LOOPCTRL_RSRVD3 21 +#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000 +#define BF_POWER_LOOPCTRL_RSRVD3(v) \ + (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3) +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000 +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \ + (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE) +#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800 +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x00000700 +#define BF_POWER_LOOPCTRL_DC_FF(v) \ + (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0x000000F0 +#define BF_POWER_LOOPCTRL_DC_R(v) \ + (((v) << 4) & BM_POWER_LOOPCTRL_DC_R) +#define BP_POWER_LOOPCTRL_RSRVD1 2 +#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C +#define BF_POWER_LOOPCTRL_RSRVD1(v) \ + (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x00000003 +#define BF_POWER_LOOPCTRL_DC_C(v) \ + (((v) << 0) & BM_POWER_LOOPCTRL_DC_C) + +#define HW_POWER_STS (0x000000c0) + +#define BP_POWER_STS_RSRVD3 30 +#define BM_POWER_STS_RSRVD3 0xC0000000 +#define BF_POWER_STS_RSRVD3(v) \ + (((v) << 30) & BM_POWER_STS_RSRVD3) +#define BP_POWER_STS_PWRUP_SOURCE 24 +#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000 +#define BF_POWER_STS_PWRUP_SOURCE(v) \ + (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE) +#define BP_POWER_STS_RSRVD2 22 +#define BM_POWER_STS_RSRVD2 0x00C00000 +#define BF_POWER_STS_RSRVD2(v) \ + (((v) << 22) & BM_POWER_STS_RSRVD2) +#define BP_POWER_STS_PSWITCH 20 +#define BM_POWER_STS_PSWITCH 0x00300000 +#define BF_POWER_STS_PSWITCH(v) \ + (((v) << 20) & BM_POWER_STS_PSWITCH) +#define BM_POWER_STS_THERMAL_WARNING 0x00080000 +#define BM_POWER_STS_VDDMEM_BO 0x00040000 +#define BM_POWER_STS_AVALID0_STATUS 0x00020000 +#define BM_POWER_STS_BVALID0_STATUS 0x00010000 +#define BM_POWER_STS_VBUSVALID0_STATUS 0x00008000 +#define BM_POWER_STS_SESSEND0_STATUS 0x00004000 +#define BM_POWER_STS_BATT_BO 0x00002000 +#define BM_POWER_STS_VDD5V_FAULT 0x00001000 +#define BM_POWER_STS_CHRGSTS 0x00000800 +#define BM_POWER_STS_DCDC_4P2_BO 0x00000400 +#define BM_POWER_STS_DC_OK 0x00000200 +#define BM_POWER_STS_VDDIO_BO 0x00000100 +#define BM_POWER_STS_VDDA_BO 0x00000080 +#define BM_POWER_STS_VDDD_BO 0x00000040 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020 +#define BM_POWER_STS_VDD5V_DROOP 0x00000010 +#define BM_POWER_STS_AVALID0 0x00000008 +#define BM_POWER_STS_BVALID0 0x00000004 +#define BM_POWER_STS_VBUSVALID0 0x00000002 +#define BM_POWER_STS_SESSEND0 0x00000001 + +#define HW_POWER_SPEED (0x000000d0) +#define HW_POWER_SPEED_SET (0x000000d4) +#define HW_POWER_SPEED_CLR (0x000000d8) +#define HW_POWER_SPEED_TOG (0x000000dc) + +#define BP_POWER_SPEED_RSRVD1 24 +#define BM_POWER_SPEED_RSRVD1 0xFF000000 +#define BF_POWER_SPEED_RSRVD1(v) \ + (((v) << 24) & BM_POWER_SPEED_RSRVD1) +#define BP_POWER_SPEED_STATUS 8 +#define BM_POWER_SPEED_STATUS 0x00FFFF00 +#define BF_POWER_SPEED_STATUS(v) \ + (((v) << 8) & BM_POWER_SPEED_STATUS) +#define BP_POWER_SPEED_STATUS_SEL 6 +#define BM_POWER_SPEED_STATUS_SEL 0x000000C0 +#define BF_POWER_SPEED_STATUS_SEL(v) \ + (((v) << 6) & BM_POWER_SPEED_STATUS_SEL) +#define BV_POWER_SPEED_STATUS_SEL__DCDC_STAT 0x0 +#define BV_POWER_SPEED_STATUS_SEL__CORE_STAT 0x1 +#define BV_POWER_SPEED_STATUS_SEL__ARM_STAT 0x2 +#define BP_POWER_SPEED_RSRVD0 2 +#define BM_POWER_SPEED_RSRVD0 0x0000003C +#define BF_POWER_SPEED_RSRVD0(v) \ + (((v) << 2) & BM_POWER_SPEED_RSRVD0) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x00000003 +#define BF_POWER_SPEED_CTRL(v) \ + (((v) << 0) & BM_POWER_SPEED_CTRL) + +#define HW_POWER_BATTMONITOR (0x000000e0) + +#define BP_POWER_BATTMONITOR_RSRVD3 26 +#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000 +#define BF_POWER_BATTMONITOR_RSRVD3(v) \ + (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) \ + (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL) +#define BP_POWER_BATTMONITOR_RSRVD2 12 +#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F000 +#define BF_POWER_BATTMONITOR_RSRVD2(v) \ + (((v) << 12) & BM_POWER_BATTMONITOR_RSRVD2) +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_ENABLE 0x00000800 +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100 +#define BP_POWER_BATTMONITOR_RSRVD1 5 +#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0 +#define BF_POWER_BATTMONITOR_RSRVD1(v) \ + (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \ + (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL) + +#define HW_POWER_RESET (0x00000100) +#define HW_POWER_RESET_SET (0x00000104) +#define HW_POWER_RESET_CLR (0x00000108) +#define HW_POWER_RESET_TOG (0x0000010c) + +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xFFFF0000 +#define BF_POWER_RESET_UNLOCK(v) \ + (((v) << 16) & BM_POWER_RESET_UNLOCK) +#define BV_POWER_RESET_UNLOCK__KEY 0x3E77 +#define BP_POWER_RESET_RSRVD1 3 +#define BM_POWER_RESET_RSRVD1 0x0000FFF8 +#define BF_POWER_RESET_RSRVD1(v) \ + (((v) << 3) & BM_POWER_RESET_RSRVD1) +#define BM_POWER_RESET_FASTFALLPSWITCH_OFF 0x00000004 +#define BM_POWER_RESET_PWD_OFF 0x00000002 +#define BM_POWER_RESET_PWD 0x00000001 + +#define HW_POWER_DEBUG (0x00000110) +#define HW_POWER_DEBUG_SET (0x00000114) +#define HW_POWER_DEBUG_CLR (0x00000118) +#define HW_POWER_DEBUG_TOG (0x0000011c) + +#define BP_POWER_DEBUG_RSRVD0 4 +#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0 +#define BF_POWER_DEBUG_RSRVD0(v) \ + (((v) << 4) & BM_POWER_DEBUG_RSRVD0) +#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001 + +#define HW_POWER_THERMAL (0x00000120) +#define HW_POWER_THERMAL_SET (0x00000124) +#define HW_POWER_THERMAL_CLR (0x00000128) +#define HW_POWER_THERMAL_TOG (0x0000012c) + +#define BP_POWER_THERMAL_RSRVD0 9 +#define BM_POWER_THERMAL_RSRVD0 0xFFFFFE00 +#define BF_POWER_THERMAL_RSRVD0(v) \ + (((v) << 9) & BM_POWER_THERMAL_RSRVD0) +#define BM_POWER_THERMAL_TEST 0x00000100 +#define BM_POWER_THERMAL_PWD 0x00000080 +#define BM_POWER_THERMAL_LOW_POWER 0x00000040 +#define BP_POWER_THERMAL_OFFSET_ADJ 4 +#define BM_POWER_THERMAL_OFFSET_ADJ 0x00000030 +#define BF_POWER_THERMAL_OFFSET_ADJ(v) \ + (((v) << 4) & BM_POWER_THERMAL_OFFSET_ADJ) +#define BM_POWER_THERMAL_OFFSET_ADJ_ENABLE 0x00000008 +#define BP_POWER_THERMAL_TEMP_THRESHOLD 0 +#define BM_POWER_THERMAL_TEMP_THRESHOLD 0x00000007 +#define BF_POWER_THERMAL_TEMP_THRESHOLD(v) \ + (((v) << 0) & BM_POWER_THERMAL_TEMP_THRESHOLD) + +#define HW_POWER_USB1CTRL (0x00000130) +#define HW_POWER_USB1CTRL_SET (0x00000134) +#define HW_POWER_USB1CTRL_CLR (0x00000138) +#define HW_POWER_USB1CTRL_TOG (0x0000013c) + +#define BP_POWER_USB1CTRL_RSRVD0 4 +#define BM_POWER_USB1CTRL_RSRVD0 0xFFFFFFF0 +#define BF_POWER_USB1CTRL_RSRVD0(v) \ + (((v) << 4) & BM_POWER_USB1CTRL_RSRVD0) +#define BM_POWER_USB1CTRL_AVALID1 0x00000008 +#define BM_POWER_USB1CTRL_BVALID1 0x00000004 +#define BM_POWER_USB1CTRL_VBUSVALID1 0x00000002 +#define BM_POWER_USB1CTRL_SESSEND1 0x00000001 + +#define HW_POWER_SPECIAL (0x00000140) +#define HW_POWER_SPECIAL_SET (0x00000144) +#define HW_POWER_SPECIAL_CLR (0x00000148) +#define HW_POWER_SPECIAL_TOG (0x0000014c) + +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF +#define BF_POWER_SPECIAL_TEST(v) (v) + +#define HW_POWER_VERSION (0x00000150) + +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xFF000000 +#define BF_POWER_VERSION_MAJOR(v) \ + (((v) << 24) & BM_POWER_VERSION_MAJOR) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0x00FF0000 +#define BF_POWER_VERSION_MINOR(v) \ + (((v) << 16) & BM_POWER_VERSION_MINOR) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0x0000FFFF +#define BF_POWER_VERSION_STEP(v) \ + (((v) << 0) & BM_POWER_VERSION_STEP) + +#define HW_POWER_ANACLKCTRL (0x00000160) +#define HW_POWER_ANACLKCTRL_SET (0x00000164) +#define HW_POWER_ANACLKCTRL_CLR (0x00000168) +#define HW_POWER_ANACLKCTRL_TOG (0x0000016c) + +#define BM_POWER_ANACLKCTRL_CKGATE_O 0x80000000 +#define BP_POWER_ANACLKCTRL_OUTDIV 28 +#define BM_POWER_ANACLKCTRL_OUTDIV 0x70000000 +#define BF_POWER_ANACLKCTRL_OUTDIV(v) \ + (((v) << 28) & BM_POWER_ANACLKCTRL_OUTDIV) +#define BM_POWER_ANACLKCTRL_INVERT_OUTCLK 0x08000000 +#define BM_POWER_ANACLKCTRL_CKGATE_I 0x04000000 +#define BP_POWER_ANACLKCTRL_RSRVD4 11 +#define BM_POWER_ANACLKCTRL_RSRVD4 0x03FFF800 +#define BF_POWER_ANACLKCTRL_RSRVD4(v) \ + (((v) << 11) & BM_POWER_ANACLKCTRL_RSRVD4) +#define BM_POWER_ANACLKCTRL_DITHER_OFF 0x00000400 +#define BM_POWER_ANACLKCTRL_SLOW_DITHER 0x00000200 +#define BM_POWER_ANACLKCTRL_INVERT_INCLK 0x00000100 +#define BP_POWER_ANACLKCTRL_RSRVD3 6 +#define BM_POWER_ANACLKCTRL_RSRVD3 0x000000C0 +#define BF_POWER_ANACLKCTRL_RSRVD3(v) \ + (((v) << 6) & BM_POWER_ANACLKCTRL_RSRVD3) +#define BP_POWER_ANACLKCTRL_INCLK_SHIFT 4 +#define BM_POWER_ANACLKCTRL_INCLK_SHIFT 0x00000030 +#define BF_POWER_ANACLKCTRL_INCLK_SHIFT(v) \ + (((v) << 4) & BM_POWER_ANACLKCTRL_INCLK_SHIFT) +#define BM_POWER_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_POWER_ANACLKCTRL_INDIV 0 +#define BM_POWER_ANACLKCTRL_INDIV 0x00000007 +#define BF_POWER_ANACLKCTRL_INDIV(v) \ + (((v) << 0) & BM_POWER_ANACLKCTRL_INDIV) + +#define HW_POWER_REFCTRL (0x00000170) +#define HW_POWER_REFCTRL_SET (0x00000174) +#define HW_POWER_REFCTRL_CLR (0x00000178) +#define HW_POWER_REFCTRL_TOG (0x0000017c) + +#define BP_POWER_REFCTRL_RSRVD5 27 +#define BM_POWER_REFCTRL_RSRVD5 0xF8000000 +#define BF_POWER_REFCTRL_RSRVD5(v) \ + (((v) << 27) & BM_POWER_REFCTRL_RSRVD5) +#define BM_POWER_REFCTRL_FASTSETTLING 0x04000000 +#define BM_POWER_REFCTRL_RAISE_REF 0x02000000 +#define BM_POWER_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define BM_POWER_REFCTRL_RSRVD4 0x00800000 +#define BP_POWER_REFCTRL_VBG_ADJ 20 +#define BM_POWER_REFCTRL_VBG_ADJ 0x00700000 +#define BF_POWER_REFCTRL_VBG_ADJ(v) \ + (((v) << 20) & BM_POWER_REFCTRL_VBG_ADJ) +#define BM_POWER_REFCTRL_LOW_PWR 0x00080000 +#define BM_POWER_REFCTRL_RSRVD3 0x00040000 +#define BP_POWER_REFCTRL_BIAS_CTRL 16 +#define BM_POWER_REFCTRL_BIAS_CTRL 0x00030000 +#define BF_POWER_REFCTRL_BIAS_CTRL(v) \ + (((v) << 16) & BM_POWER_REFCTRL_BIAS_CTRL) +#define BM_POWER_REFCTRL_RSRVD2 0x00008000 +#define BM_POWER_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 +#define BM_POWER_REFCTRL_ADJ_ANA 0x00002000 +#define BM_POWER_REFCTRL_ADJ_VAG 0x00001000 +#define BP_POWER_REFCTRL_ANA_REFVAL 8 +#define BM_POWER_REFCTRL_ANA_REFVAL 0x00000F00 +#define BF_POWER_REFCTRL_ANA_REFVAL(v) \ + (((v) << 8) & BM_POWER_REFCTRL_ANA_REFVAL) +#define BP_POWER_REFCTRL_VAG_VAL 4 +#define BM_POWER_REFCTRL_VAG_VAL 0x000000F0 +#define BF_POWER_REFCTRL_VAG_VAL(v) \ + (((v) << 4) & BM_POWER_REFCTRL_VAG_VAL) +#define BP_POWER_REFCTRL_RSRVD1 0 +#define BM_POWER_REFCTRL_RSRVD1 0x0000000F +#define BF_POWER_REFCTRL_RSRVD1(v) \ + (((v) << 0) & BM_POWER_REFCTRL_RSRVD1) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pwm.h b/arch/arm/mach-mx28/include/mach/regs-pwm.h new file mode 100644 index 000000000000..ac0ebfbb7cca --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pwm.h @@ -0,0 +1,147 @@ +/* + * Freescale PWM Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H + +#include <mach/mx28.h> + +#define REGS_PWM_BASE IO_ADDRESS(PWM_PHYS_ADDR) +#define REGS_PWM_PHYS (0x80064000) +#define REGS_PWM_SIZE 0x00002000 + +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) + +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM7_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM6_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM5_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x02000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x01000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x00800000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x00400000 +#define BP_PWM_CTRL_RSRVD1 10 +#define BM_PWM_CTRL_RSRVD1 0x003FFC00 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000200 +#define BM_PWM_CTRL_RSRVD2 0x00000100 +#define BM_PWM_CTRL_PWM7_ENABLE 0x00000080 +#define BM_PWM_CTRL_PWM6_ENABLE 0x00000040 +#define BM_PWM_CTRL_PWM5_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 8 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 8 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_PWM_PERIODn_RSRVD2 27 +#define BM_PWM_PERIODn_RSRVD2 0xF8000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 27) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_HSADC_OUT 0x04000000 +#define BM_PWM_PERIODn_HSADC_CLK_SEL 0x02000000 +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 +#define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x00000110) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pxp.h b/arch/arm/mach-mx28/include/mach/regs-pxp.h new file mode 100644 index 000000000000..2feb8f8db649 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pxp.h @@ -0,0 +1,518 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BP_PXP_CTRL_RSVD2 28 +#define BM_PXP_CTRL_RSVD2 0x30000000 +#define BF_PXP_CTRL_RSVD2(v) \ + (((v) << 28) & BM_PXP_CTRL_RSVD2) +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_S0_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_S0_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_S0_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_S0_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTBUF_FORMAT 4 +#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT) +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444 0x7 +#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUTBUF (0x00000020) + +#define BP_PXP_OUTBUF_ADDR 0 +#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF_ADDR(v) (v) + +#define HW_PXP_OUTBUF2 (0x00000030) + +#define BP_PXP_OUTBUF2_ADDR 0 +#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF2_ADDR(v) (v) + +#define HW_PXP_OUTSIZE (0x00000040) + +#define BP_PXP_OUTSIZE_ALPHA 24 +#define BM_PXP_OUTSIZE_ALPHA 0xFF000000 +#define BF_PXP_OUTSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUTSIZE_ALPHA) +#define BP_PXP_OUTSIZE_WIDTH 12 +#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000 +#define BF_PXP_OUTSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_OUTSIZE_WIDTH) +#define BP_PXP_OUTSIZE_HEIGHT 0 +#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF +#define BF_PXP_OUTSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OUTSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BM_PXP_S0SCALE_RSVD2 0x80000000 +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BM_PXP_S0SCALE_RSVD1 0x00008000 +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00007FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEFF0 (0x000000d0) + +#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 +#define BP_PXP_CSCCOEFF0_RSVD1 29 +#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 +#define BF_PXP_CSCCOEFF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1) +#define BP_PXP_CSCCOEFF0_C0 18 +#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEFF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEFF0_C0) +#define BP_PXP_CSCCOEFF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET) +#define BP_PXP_CSCCOEFF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET) + +#define HW_PXP_CSCCOEFF1 (0x000000e0) + +#define BP_PXP_CSCCOEFF1_RSVD1 27 +#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1) +#define BP_PXP_CSCCOEFF1_C1 16 +#define BM_PXP_CSCCOEFF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF1_C1) +#define BP_PXP_CSCCOEFF1_RSVD0 11 +#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0) +#define BP_PXP_CSCCOEFF1_C4 0 +#define BM_PXP_CSCCOEFF1_C4 0x000007FF +#define BF_PXP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF1_C4) + +#define HW_PXP_CSCCOEFF2 (0x000000f0) + +#define BP_PXP_CSCCOEFF2_RSVD1 27 +#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1) +#define BP_PXP_CSCCOEFF2_C2 16 +#define BM_PXP_CSCCOEFF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF2_C2) +#define BP_PXP_CSCCOEFF2_RSVD0 11 +#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0) +#define BP_PXP_CSCCOEFF2_C3 0 +#define BM_PXP_CSCCOEFF2_C3 0x000007FF +#define BF_PXP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 9 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD) +#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__TLBCOUNT 0xF0 +#define BV_PXP_DEBUGCTRL_SELECT__TLBHIT 0xF1 +#define BV_PXP_DEBUGCTRL_SELECT__TLBMISS 0xF2 +#define BV_PXP_DEBUGCTRL_SELECT__TLBLAT 0xF3 +#define BV_PXP_DEBUGCTRL_SELECT__TLBSTATE 0xF8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-rtc.h b/arch/arm/mach-mx28/include/mach/regs-rtc.h new file mode 100644 index 000000000000..bdb3ac23a2a0 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-rtc.h @@ -0,0 +1,226 @@ +/* + * Freescale RTC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.75 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H + + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 +#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) + +#define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) + +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) + +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) + +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) + +#define BP_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 28 +#define BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 0xF0000000 +#define BF_RTC_PERSISTENT0_ADJ_POSLIMITBUCK(v) \ + (((v) << 28) & BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK) +#define BP_RTC_PERSISTENT0_SPARE_ANALOG 22 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0x0FC00000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 22) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_EXTERNAL_RESET 0x00200000 +#define BM_RTC_PERSISTENT0_THERMAL_RESET 0x00100000 +#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000 +#define BM_RTC_PERSISTENT0_ENABLE_LRADC_PWRUP 0x00040000 +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) + +#define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) + +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ssp.h b/arch/arm/mach-mx28/include/mach/regs-ssp.h new file mode 100644 index 000000000000..1d4793b25a3b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ssp.h @@ -0,0 +1,474 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 4.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_RSVD0 0 +#define BM_SSP_CTRL0_RSVD0 0x0000FFFF +#define BF_SSP_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_SSP_CTRL0_RSVD0) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 27 +#define BM_SSP_CMD0_RSVD0 0xF8000000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 27) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000 +#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000 +#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000 +#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000 +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_RSVD1 8 +#define BM_SSP_CMD0_RSVD1 0x000FFF00 +#define BF_SSP_CMD0_RSVD1(v) \ + (((v) << 8) & BM_SSP_CMD0_RSVD1) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_XFER_SIZE (0x00000030) + +#define BP_SSP_XFER_SIZE_XFER_COUNT 0 +#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF +#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v) + +#define HW_SSP_BLOCK_SIZE (0x00000040) + +#define BP_SSP_BLOCK_SIZE_RSVD0 28 +#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000 +#define BF_SSP_BLOCK_SIZE_RSVD0(v) \ + (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0) +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0 +#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \ + (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT) +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F +#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \ + (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE) + +#define HW_SSP_COMPREF (0x00000050) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000060) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000070) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000080) +#define HW_SSP_CTRL1_SET (0x00000084) +#define HW_SSP_CTRL1_CLR (0x00000088) +#define HW_SSP_CTRL1_TOG (0x0000008c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA (0x00000090) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x000000a0) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x000000b0) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000c0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000d0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_DDR_CTRL (0x000000e0) + +#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30 +#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000 +#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \ + (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE) +#define BP_SSP_DDR_CTRL_RSVD0 2 +#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC +#define BF_SSP_DDR_CTRL_RSVD0(v) \ + (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0) +#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002 +#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001 + +#define HW_SSP_DLL_CTRL (0x000000f0) + +#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT) +#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT) +#define BP_SSP_DLL_CTRL_RSVD1 16 +#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000 +#define BF_SSP_DLL_CTRL_RSVD1(v) \ + (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1) +#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00 +#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_SSP_DLL_CTRL_RSVD0 0x00000100 +#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET) +#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_SSP_DLL_CTRL_RESET 0x00000002 +#define BM_SSP_DLL_CTRL_ENABLE 0x00000001 + +#define HW_SSP_STATUS (0x00000100) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 23 +#define BM_SSP_STATUS_RSVD3 0x0F800000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 23) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMABURST 0x00400000 +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DLL_STS (0x00000110) + +#define BP_SSP_DLL_STS_RSVD0 14 +#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000 +#define BF_SSP_DLL_STS_RSVD0(v) \ + (((v) << 14) & BM_SSP_DLL_STS_RSVD0) +#define BP_SSP_DLL_STS_REF_SEL 8 +#define BM_SSP_DLL_STS_REF_SEL 0x00003F00 +#define BF_SSP_DLL_STS_REF_SEL(v) \ + (((v) << 8) & BM_SSP_DLL_STS_REF_SEL) +#define BP_SSP_DLL_STS_SLV_SEL 2 +#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC +#define BF_SSP_DLL_STS_SLV_SEL(v) \ + (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL) +#define BM_SSP_DLL_STS_REF_LOCK 0x00000002 +#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_SSP_DEBUG (0x00000120) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000130) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-timrot.h b/arch/arm/mach-mx28/include/mach/regs-timrot.h new file mode 100644 index 000000000000..125b835e19ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-timrot.h @@ -0,0 +1,293 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.40 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40) +#define BP_TIMROT_TIMCTRLn_RSRVD3 16 +#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD2 12 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF + +/* + * multi-register-define name HW_TIMROT_RUNNING_COUNTn + * base 0x00000030 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40) +#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_FIXED_COUNTn + * base 0x00000040 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40) +#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_MATCH_COUNTn + * base 0x00000050 + * count 4 + * offset 0x40 + */ +#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40) +#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0 +#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF +#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v) + +#define HW_TIMROT_TIMCTRL3 (0x000000e0) +#define HW_TIMROT_TIMCTRL3_SET (0x000000e4) +#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8) +#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 12 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF + +#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0) + +#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v) + +#define HW_TIMROT_FIXED_COUNT3 (0x00000100) + +#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v) + +#define HW_TIMROT_VERSION (0x00000120) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx28/include/mach/regulator.h b/arch/arm/mach-mx28/include/mach/regulator.h new file mode 100644 index 000000000000..1b073586268b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regulator.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __PLAT_REGULATOR_H_ +#define __PLAT_REGULATOR_H_ + +#define MXS_REG5V_NOT_USB 0 +#define MXS_REG5V_IS_USB 1 +#define MXS_VDDD 0 +#define MXS_VDDA 1 +#define MXS_VDDIO 2 +#define MXS_VDDDBO 3 +#define MXS_OVERALL_CUR 4 + +#endif diff --git a/arch/arm/mach-mx28/mx28_pins.h b/arch/arm/mach-mx28/mx28_pins.h new file mode 100644 index 000000000000..a87ab9d6fc81 --- /dev/null +++ b/arch/arm/mach-mx28/mx28_pins.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +#include <mach/pinctrl.h> + +/* + * Define MX28 pins, the pin name corresponds to MX28 hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0) +#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1) +#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2) +#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3) +#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4) +#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5) +#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6) +#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7) +#define PINID_GPMI_CE0N MXS_PIN_ENCODE(0, 16) +#define PINID_GPMI_CE1N MXS_PIN_ENCODE(0, 17) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_CE3N MXS_PIN_ENCODE(0, 19) +#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 20) +#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 21) +#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 22) +#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 23) +#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 24) +#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 25) +#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 26) +#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 27) +#define PINID_GPMI_RESETN MXS_PIN_ENCODE(0, 28) + +/* Bank 1 */ +#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0) +#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1) +#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2) +#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3) +#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4) +#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5) +#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6) +#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7) +#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8) +#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9) +#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10) +#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11) +#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12) +#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13) +#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14) +#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15) +#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16) +#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17) +#define PINID_LCD_D18 MXS_PIN_ENCODE(1, 18) +#define PINID_LCD_D19 MXS_PIN_ENCODE(1, 19) +#define PINID_LCD_D20 MXS_PIN_ENCODE(1, 20) +#define PINID_LCD_D21 MXS_PIN_ENCODE(1, 21) +#define PINID_LCD_D22 MXS_PIN_ENCODE(1, 22) +#define PINID_LCD_D23 MXS_PIN_ENCODE(1, 23) +#define PINID_LCD_RD_E MXS_PIN_ENCODE(1, 24) +#define PINID_LCD_WR_RWN MXS_PIN_ENCODE(1, 25) +#define PINID_LCD_RS MXS_PIN_ENCODE(1, 26) +#define PINID_LCD_CS MXS_PIN_ENCODE(1, 27) +#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 28) +#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 29) +#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 30) +#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 31) + +/* Bank 2 */ +#define PINID_SSP0_DATA0 MXS_PIN_ENCODE(2, 0) +#define PINID_SSP0_DATA1 MXS_PIN_ENCODE(2, 1) +#define PINID_SSP0_DATA2 MXS_PIN_ENCODE(2, 2) +#define PINID_SSP0_DATA3 MXS_PIN_ENCODE(2, 3) +#define PINID_SSP0_DATA4 MXS_PIN_ENCODE(2, 4) +#define PINID_SSP0_DATA5 MXS_PIN_ENCODE(2, 5) +#define PINID_SSP0_DATA6 MXS_PIN_ENCODE(2, 6) +#define PINID_SSP0_DATA7 MXS_PIN_ENCODE(2, 7) +#define PINID_SSP0_CMD MXS_PIN_ENCODE(2, 8) +#define PINID_SSP0_DETECT MXS_PIN_ENCODE(2, 9) +#define PINID_SSP0_SCK MXS_PIN_ENCODE(2, 10) +#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 12) +#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 13) +#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 14) +#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 15) +#define PINID_SSP2_SCK MXS_PIN_ENCODE(2, 16) +#define PINID_SSP2_MOSI MXS_PIN_ENCODE(2, 17) +#define PINID_SSP2_MISO MXS_PIN_ENCODE(2, 18) +#define PINID_SSP2_SS0 MXS_PIN_ENCODE(2, 19) +#define PINID_SSP2_SS1 MXS_PIN_ENCODE(2, 20) +#define PINID_SSP2_SS2 MXS_PIN_ENCODE(2, 21) +#define PINID_SSP3_SCK MXS_PIN_ENCODE(2, 24) +#define PINID_SSP3_MOSI MXS_PIN_ENCODE(2, 25) +#define PINID_SSP3_MISO MXS_PIN_ENCODE(2, 26) +#define PINID_SSP3_SS0 MXS_PIN_ENCODE(2, 27) + +/* Bank 3 */ +#define PINID_AUART0_RX MXS_PIN_ENCODE(3, 0) +#define PINID_AUART0_TX MXS_PIN_ENCODE(3, 1) +#define PINID_AUART0_CTS MXS_PIN_ENCODE(3, 2) +#define PINID_AUART0_RTS MXS_PIN_ENCODE(3, 3) +#define PINID_AUART1_RX MXS_PIN_ENCODE(3, 4) +#define PINID_AUART1_TX MXS_PIN_ENCODE(3, 5) +#define PINID_AUART1_CTS MXS_PIN_ENCODE(3, 6) +#define PINID_AUART1_RTS MXS_PIN_ENCODE(3, 7) +#define PINID_AUART2_RX MXS_PIN_ENCODE(3, 8) +#define PINID_AUART2_TX MXS_PIN_ENCODE(3, 9) +#define PINID_AUART2_CTS MXS_PIN_ENCODE(3, 10) +#define PINID_AUART2_RTS MXS_PIN_ENCODE(3, 11) +#define PINID_AUART3_RX MXS_PIN_ENCODE(3, 12) +#define PINID_AUART3_TX MXS_PIN_ENCODE(3, 13) +#define PINID_AUART3_CTS MXS_PIN_ENCODE(3, 14) +#define PINID_AUART3_RTS MXS_PIN_ENCODE(3, 15) +#define PINID_PWM0 MXS_PIN_ENCODE(3, 16) +#define PINID_PWM1 MXS_PIN_ENCODE(3, 17) +#define PINID_PWM2 MXS_PIN_ENCODE(3, 18) +#define PINID_SAIF0_MCLK MXS_PIN_ENCODE(3, 20) +#define PINID_SAIF0_LRCLK MXS_PIN_ENCODE(3, 21) +#define PINID_SAIF0_BITCLK MXS_PIN_ENCODE(3, 22) +#define PINID_SAIF0_SDATA0 MXS_PIN_ENCODE(3, 23) +#define PINID_I2C0_SCL MXS_PIN_ENCODE(3, 24) +#define PINID_I2C0_SDA MXS_PIN_ENCODE(3, 25) +#define PINID_SAIF1_SDATA0 MXS_PIN_ENCODE(3, 26) +#define PINID_SPDIF MXS_PIN_ENCODE(3, 27) +#define PINID_PWM3 MXS_PIN_ENCODE(3, 28) +#define PINID_PWM4 MXS_PIN_ENCODE(3, 29) +#define PINID_LCD_RESET MXS_PIN_ENCODE(3, 30) + +/* Bank 4 */ +#define PINID_ENET0_MDC MXS_PIN_ENCODE(4, 0) +#define PINID_ENET0_MDIO MXS_PIN_ENCODE(4, 1) +#define PINID_ENET0_RX_EN MXS_PIN_ENCODE(4, 2) +#define PINID_ENET0_RXD0 MXS_PIN_ENCODE(4, 3) +#define PINID_ENET0_RXD1 MXS_PIN_ENCODE(4, 4) +#define PINID_ENET0_TX_CLK MXS_PIN_ENCODE(4, 5) +#define PINID_ENET0_TX_EN MXS_PIN_ENCODE(4, 6) +#define PINID_ENET0_TXD0 MXS_PIN_ENCODE(4, 7) +#define PINID_ENET0_TXD1 MXS_PIN_ENCODE(4, 8) +#define PINID_ENET0_RXD2 MXS_PIN_ENCODE(4, 9) +#define PINID_ENET0_RXD3 MXS_PIN_ENCODE(4, 10) +#define PINID_ENET0_TXD2 MXS_PIN_ENCODE(4, 11) +#define PINID_ENET0_TXD3 MXS_PIN_ENCODE(4, 12) +#define PINID_ENET0_RX_CLK MXS_PIN_ENCODE(4, 13) +#define PINID_ENET0_COL MXS_PIN_ENCODE(4, 14) +#define PINID_ENET0_CRS MXS_PIN_ENCODE(4, 15) +#define PINID_ENET_CLK MXS_PIN_ENCODE(4, 16) +#define PINID_JTAG_RTCK MXS_PIN_ENCODE(4, 20) +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c new file mode 100644 index 000000000000..97ce49c20d9d --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/pinctrl.h> + +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> + +#include "device.h" +#include "mx28evk.h" + +static struct i2c_board_info __initdata mxs_i2c_device[] = { + { I2C_BOARD_INFO("sgtl5000-i2c", 0xa), .flags = I2C_M_TEN } +}; + +static void __init i2c_device_init(void) +{ + i2c_register_board_info(0, mxs_i2c_device, ARRAY_SIZE(mxs_i2c_device)); +} +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +static struct flash_platform_data mx28_spi_flash_data = { + .name = "m25p80", + .type = "w25x80", +}; +#endif + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, /* Framework bus number */ + .chip_select = 0, /* Framework chip select. */ + .platform_data = &mx28_spi_flash_data, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init fixup_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mx28_set_input_clk(24000000, 24000000, 32000, 50000000); +} + +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) +static struct mxs_pwm_led mx28evk_led_pwm[2] = { + [0] = { + .name = "led-pwm0", + .pwm = 0, + }, + [1] = { + .name = "led-pwm1", + .pwm = 1, + }, +}; + +struct mxs_pwm_leds_plat_data mx28evk_led_data = { + .num = ARRAY_SIZE(mx28evk_led_pwm), + .leds = mx28evk_led_pwm, +}; + +static struct resource mx28evk_led_res = { + .flags = IORESOURCE_MEM, + .start = PWM_PHYS_ADDR, + .end = PWM_PHYS_ADDR + 0x3FFF, +}; + +static void __init mx28evk_init_leds(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-leds", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = &mx28evk_led_res; + pdev->num_resources = 1; + pdev->dev.platform_data = &mx28evk_led_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28evk_init_leds(void) +{ + ; +} +#endif + +static void __init mx28evk_device_init(void) +{ + /* Add mx28evk special code */ + i2c_device_init(); + spi_device_init(); + mx28evk_init_leds(); +} + +static void __init mx28evk_init_machine(void) +{ + mx28_pinctrl_init(); + /* Init iram allocate */ +#ifdef CONFIG_VECTORS_PHY_ADDR + /* reserve the first page for irq vector table*/ + iram_init(MX28_OCRAM_PHBASE + PAGE_SIZE, MX28_OCRAM_SIZE - PAGE_SIZE); +#else + iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE); +#endif + + mx28_gpio_init(); + mx28evk_pins_init(); + mx28_device_init(); + mx28evk_device_init(); + + /* init the system revesion */ + system_rev = 0x28011; +} + +MACHINE_START(MX28EVK, "Freescale MX28EVK board") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .fixup = fixup_board, + .map_io = mx28_map_io, + .init_irq = mx28_irq_init, + .init_machine = mx28evk_init_machine, + .timer = &mx28_timer.timer, +MACHINE_END diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h new file mode 100644 index 000000000000..d973c0f7ef19 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_MACH_MX28EVK_H +#define __ASM_ARM_MACH_MX28EVK_H + +extern void __init mx28evk_pins_init(void); +extern int mx28evk_enet_gpio_init(void); +void mx28evk_enet_io_lowerpower_enter(void); +void mx28evk_enet_io_lowerpower_exit(void); + + +#endif /* __ASM_ARM_MACH_MX28EVK_H */ diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c new file mode 100644 index 000000000000..1990b925f681 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk_pins.c @@ -0,0 +1,1231 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/delay.h> + +#include <mach/pinctrl.h> + +#include "mx28_pins.h" + +static struct pin_desc mx28evk_fixed_pins[] = { + { + .name = "DUART.RX", + .id = PINID_PWM0, + .fun = PIN_FUN3, + }, + { + .name = "DUART.TX", + .id = PINID_PWM1, + .fun = PIN_FUN3, + }, +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + { + .name = "AUART0.RX", + .id = PINID_AUART0_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.TX", + .id = PINID_AUART0_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.CTS", + .id = PINID_AUART0_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.RTS", + .id = PINID_AUART0_RTS, + .fun = PIN_FUN1, + }, +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + { + .name = "AUART3.RX", + .id = PINID_AUART3_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.TX", + .id = PINID_AUART3_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.CTS", + .id = PINID_AUART3_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.RTS", + .id = PINID_AUART3_RTS, + .fun = PIN_FUN1, + }, +#endif + { + .name = "usb0", + .id = PINID_AUART2_TX, /* Power enable pin*/ + .fun = PIN_GPIO, + .data = 0, + .output = 1, + }, + { + .name = "usb1", + .id = PINID_AUART2_RX, + .fun = PIN_GPIO, + .data = 1, + .output = 1, + }, + +#if defined(CONFIG_USB_OTG) + { + .name = "usb0_id", + .id = PINID_AUART1_RTS, + .fun = PIN_FUN2, + .data = 1, + .pull = 1, + .pullup = 1, + }, +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) + { + .name = "CAN1_TX", + .id = PINID_GPMI_CE2N, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN1_RX", + .id = PINID_GPMI_CE3N, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN0_TX", + .id = PINID_GPMI_RDY2, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN0_RX", + .id = PINID_GPMI_RDY3, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN_PWDN", + .id = PINID_SSP1_CMD, + .fun = PIN_GPIO, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + .data = 0, + .output = 1, + }, + +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) + { + .name = "I2C0_SCL", + .id = PINID_I2C0_SCL, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "I2C0_SDA", + .id = PINID_I2C0_SDA, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) + { + .name = "LCD_D00", + .id = PINID_LCD_D00, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D01", + .id = PINID_LCD_D01, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D02", + .id = PINID_LCD_D02, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D03", + .id = PINID_LCD_D03, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D04", + .id = PINID_LCD_D04, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D05", + .id = PINID_LCD_D05, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D06", + .id = PINID_LCD_D06, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D07", + .id = PINID_LCD_D07, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D08", + .id = PINID_LCD_D08, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D09", + .id = PINID_LCD_D09, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D10", + .id = PINID_LCD_D10, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D11", + .id = PINID_LCD_D11, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D12", + .id = PINID_LCD_D12, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D13", + .id = PINID_LCD_D13, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D14", + .id = PINID_LCD_D14, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D15", + .id = PINID_LCD_D15, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D16", + .id = PINID_LCD_D16, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D17", + .id = PINID_LCD_D17, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D18", + .id = PINID_LCD_D18, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D19", + .id = PINID_LCD_D19, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D20", + .id = PINID_LCD_D20, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D21", + .id = PINID_LCD_D21, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D22", + .id = PINID_LCD_D22, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D23", + .id = PINID_LCD_D23, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_RESET", + .id = PINID_LCD_RESET, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_VSYNC", + .id = PINID_LCD_RD_E, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_HSYNC", + .id = PINID_LCD_WR_RWN, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_ENABLE", + .id = PINID_LCD_CS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_DOTCLK", + .id = PINID_LCD_RS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_BACKLIGHT", + .id = PINID_PWM2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) + /* Configurations of SSP0 SD/MMC port pins */ + { + .name = "SSP0_DATA0", + .id = PINID_SSP0_DATA0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA1", + .id = PINID_SSP0_DATA1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA2", + .id = PINID_SSP0_DATA2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA3", + .id = PINID_SSP0_DATA3, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA4", + .id = PINID_SSP0_DATA4, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA5", + .id = PINID_SSP0_DATA5, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA6", + .id = PINID_SSP0_DATA6, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA7", + .id = PINID_SSP0_DATA7, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_CMD", + .id = PINID_SSP0_CMD, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DETECT", + .id = PINID_SSP0_DETECT, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP0_SCK", + .id = PINID_SSP0_SCK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 2, + .pull = 0, + }, +#endif +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) + { + .name = "LEDS_PWM0", + .id = PINID_AUART1_RX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "LEDS_PWM1", + .id = PINID_AUART1_TX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) + /* Configurations of SAIF0 port pins */ + { + .name = "SAIF0_MCLK", + .id = PINID_SAIF0_MCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_LRCLK", + .id = PINID_SAIF0_LRCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_BITCLK", + .id = PINID_SAIF0_BITCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_SDATA0", + .id = PINID_SAIF0_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF1_SDATA0", + .id = PINID_SAIF1_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) + { + .name = "SPDIF", + .id = PINID_SPDIF, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +}; + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) +static struct pin_desc mx28evk_eth_pins[] = { + { + .name = "ENET0_MDC", + .id = PINID_ENET0_MDC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_MDIO", + .id = PINID_ENET0_MDIO, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RX_EN", + .id = PINID_ENET0_RX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD0", + .id = PINID_ENET0_RXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD1", + .id = PINID_ENET0_RXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TX_EN", + .id = PINID_ENET0_TX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD0", + .id = PINID_ENET0_TXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD1", + .id = PINID_ENET0_TXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RX_EN", + .id = PINID_ENET0_CRS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RXD0", + .id = PINID_ENET0_RXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RXD1", + .id = PINID_ENET0_RXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TX_EN", + .id = PINID_ENET0_COL, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TXD0", + .id = PINID_ENET0_TXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TXD1", + .id = PINID_ENET0_TXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET_CLK", + .id = PINID_ENET_CLK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + +static int __initdata enable_ssp1 = { 0 }; +static int __init ssp1_setup(char *__unused) +{ + enable_ssp1 = 1; + return 1; +} + +__setup("ssp1", ssp1_setup); + +static struct pin_desc mx28evk_ssp1_pins[] = { + { + .name = "SSP1_DATA0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DETECT", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP1_SCK", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN2, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 2, + .pull = 0, + }, +}; + + +int enable_gpmi = { 0 }; +static int __init gpmi_setup(char *__unused) +{ + enable_gpmi = 1; + return 1; +} + +__setup("gpmi", gpmi_setup); + +static struct pin_desc mx28evk_gpmi_pins[] = { + { + .name = "GPMI D0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE0-", + .id = PINID_GPMI_CE0N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE1-", + .id = PINID_GPMI_CE1N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY0", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY1", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RD-", + .id = PINID_GPMI_RDN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WR-", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI ALE", + .id = PINID_GPMI_ALE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CLE", + .id = PINID_GPMI_CLE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RST-", + .id = PINID_GPMI_RESETN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, +}; + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct pin_desc mx28evk_spi_pins[] = { + { + .name = "SSP2 MOSI", + .id = PINID_SSP2_MOSI, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 MISO", + .id = PINID_SSP2_MISO, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 SCK", + .id = PINID_SSP2_SCK, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 SS0", + .id = PINID_SSP2_SS0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) +int mx28evk_enet_gpio_init(void) +{ + /* pwr */ + gpio_request(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), "ENET_PWR"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + + /* reset phy */ + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + + /* + * Before timer bug fix(set wrong match value of timer), + * mdelay(10) delay 50ms actually. + * So change delay to 50ms after timer issue fix. + */ + mdelay(50); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + + return 0; +} + +void mx28evk_enet_io_lowerpower_enter(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 1); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), "ETH_INT"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), 0); + + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + mxs_release_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].name); + gpio_request(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), + mx28evk_eth_pins[i].name); + gpio_direction_output( + MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), 0); + } + +} + +void mx28evk_enet_io_lowerpower_exit(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + gpio_free(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK)); + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + gpio_free(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id)); + mxs_request_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].fun, + mx28evk_eth_pins[i].name); + } +} + +#else +int mx28evk_enet_gpio_init(void) +{ + return 0; +} +void mx28evk_enet_io_lowerpower_enter(void) +{} +void mx28evk_enet_io_lowerpower_exit(void) +{} +#endif + +void __init mx28evk_init_pin_group(struct pin_desc *pins, unsigned count) +{ + int i; + struct pin_desc *pin; + for (i = 0; i < count; i++) { + pin = pins + i; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->output) + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + else + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + } + } +} + +void __init mx28evk_pins_init(void) +{ + + mx28evk_init_pin_group(mx28evk_fixed_pins, + ARRAY_SIZE(mx28evk_fixed_pins)); + + if (enable_ssp1) { + pr_info("Initializing SSP1 pins\n"); + mx28evk_init_pin_group(mx28evk_ssp1_pins, + ARRAY_SIZE(mx28evk_ssp1_pins)); + } else if (enable_gpmi) { + pr_info("Initializing GPMI pins\n"); + mx28evk_init_pin_group(mx28evk_gpmi_pins, + ARRAY_SIZE(mx28evk_gpmi_pins)); + } + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) + mx28evk_init_pin_group(mx28evk_spi_pins, + ARRAY_SIZE(mx28evk_spi_pins)); +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) + mx28evk_init_pin_group(mx28evk_eth_pins, + ARRAY_SIZE(mx28evk_eth_pins)); +#endif +} diff --git a/arch/arm/mach-mx28/pinctrl.c b/arch/arm/mach-mx28/pinctrl.c new file mode 100644 index 000000000000..296f4036395d --- /dev/null +++ b/arch/arm/mach-mx28/pinctrl.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id) +{ + int bank; + bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK); + if (bank == MXS_PIN_BANK_MAX) + return -EINVAL; + *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK); + return bank; +} + +static unsigned int mx28_get_gpio(struct pin_bank *bank, unsigned int id) +{ + if (bank->gpio_port >= MXS_NON_GPIO) + return -EINVAL; + return bank->gpio_port * PINS_PER_BANK + id; +} + +static void mx28_set_strength(struct pin_bank *bank, + unsigned int id, enum pad_strength strength) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id *= 4; + __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER); + __raw_writel(strength << id, addr + SET_REGISTER); +} + +static void mx28_set_voltage(struct pin_bank *bank, + unsigned int id, enum pad_voltage volt) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id = id * 4 + 2; + if (volt == PAD_1_8V) + __raw_writel(1 << id, addr + CLR_REGISTER); + else + __raw_writel(1 << id, addr + SET_REGISTER); +} + +static void mx28_set_pullup(struct pin_bank *bank, unsigned int id, int pullup) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0; + addr += 0x10 * bank->id; + if (pullup) + __raw_writel(1 << id, addr + SET_REGISTER); + else + __raw_writel(1 << id, addr + CLR_REGISTER); +} + +static void mx28_set_type(struct pin_bank *bank, + unsigned int id, enum pin_fun cfg) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + __raw_writel(0x3 << id, addr + CLR_REGISTER); + __raw_writel(cfg << id, addr + SET_REGISTER); +} + +static int mx28_get_type(struct pin_bank *bank, + unsigned int id) +{ + void __iomem *addr; + int ret; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + ret = (__raw_readl(addr) >> id) & 0x3; + return ret; +} + +static struct pin_bank mx28_pin_banks[6] = { + [0] = { + .id = 0, + .gpio_port = 0, + }, + [1] = { + .id = 1, + .gpio_port = 1, + }, + [2] = { + .id = 2, + .gpio_port = 2, + }, + [3] = { + .id = 3, + .gpio_port = 3, + }, + [4] = { + .id = 4, + .gpio_port = 4, + }, + [5] = { + .id = 5, + .gpio_port = MXS_NON_GPIO, + } +}; + +static struct pinctrl_chip mx28_pinctrl = { + .name = "pinctrl", + .banks = mx28_pin_banks, + .pin2id = mx28_pin2id, + .get_gpio = mx28_get_gpio, + .set_strength = mx28_set_strength, + .set_voltage = mx28_set_voltage, + .set_pullup = mx28_set_pullup, + .set_type = mx28_set_type, + .get_type = mx28_get_type, +}; + +int __init mx28_pinctrl_init(void) +{ + int i; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + mx28_pinctrl.bank_size = ARRAY_SIZE(mx28_pin_banks); + return mxs_set_pinctrl_chip(&mx28_pinctrl); +} diff --git a/arch/arm/mach-mx28/pm.c b/arch/arm/mach-mx28/pm.c new file mode 100644 index 000000000000..affb0de9f312 --- /dev/null +++ b/arch/arm/mach-mx28/pm.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include <linux/suspend.h> +#include <linux/rtc.h> +#include <linux/pm.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/kthread.h> +#include <linux/slab.h> + +#include <asm/cacheflush.h> +#include <asm/mach-types.h> + +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/dma.h> +#include <mach/regs-rtc.h> +#include "regs-clkctrl.h" +#include <mach/regs-power.h> +#include <mach/regs-pwm.h> +#include <mach/regs-rtc.h> +#include <mach/../../regs-icoll.h> +#include "regs-dram.h" +#include "mx28_pins.h" +#include "mx28evk.h" + +#include "sleep.h" + +#define PENDING_IRQ_RETRY 100 +static void *saved_sram; +static int saved_sleep_state; + +#define WAIT_DC_OK_CYCLES 24000 +#define WAIT_CYCLE(n) for (i = 0; i < n; i++); +#define LOWER_VDDIO 10 +#define LOWER_VDDA 9 +#define LOWER_VDDD 0xa +#define MAX_POWEROFF_CODE_SIZE (6 * 1024) +#define REGS_CLKCTRL_BASE IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define dbgc(ch) __raw_writel(ch, IO_ADDRESS(0x80074000)); +inline void dbgnum(u32 num) +{ + dbgc((num / 1000) + '0'); + dbgc(((num%1000) / 100) + '0'); + dbgc(((num%100) / 10) + '0'); + dbgc((num%10) + '0'); + dbgc('\n'); +} + +static inline void do_standby(void) +{ + void (*mx28_cpu_standby_ptr) (void); + struct clk *cpu_clk; + struct clk *osc_clk; + struct clk *pll_clk; + struct clk *hbus_clk; + struct clk *cpu_parent = NULL; + int cpu_rate = 0; + int hbus_rate = 0; + u32 reg_clkctrl_clkseq, reg_clkctrl_xtal; + unsigned long iram_phy_addr; + void *iram_virtual_addr; + int wakeupirq; + mx28evk_enet_io_lowerpower_enter(); + /* + * 1) switch clock domains from PLL to 24MHz + * 2) lower voltage (TODO) + * 3) switch EMI to 24MHz and turn PLL off (done in sleep.S) + */ + + + /* make sure SRAM copy gets physically written into SDRAM. + * SDRAM will be placed into self-refresh during power down + */ + flush_cache_all(); + iram_virtual_addr = iram_alloc(MAX_POWEROFF_CODE_SIZE, &iram_phy_addr); + if (iram_virtual_addr == NULL) { + pr_info("can not get iram for suspend\n"); + return; + } + /* copy suspend function into SRAM */ + memcpy(iram_virtual_addr, mx28_cpu_standby, mx28_standby_alloc_sz); + + /* now switch the CPU to ref_xtal */ + cpu_clk = clk_get(NULL, "cpu"); + osc_clk = clk_get(NULL, "ref_xtal"); + pll_clk = clk_get(NULL, "pll.0"); + hbus_clk = clk_get(NULL, "h"); + + if (!IS_ERR(cpu_clk) && !IS_ERR(osc_clk)) { + cpu_rate = clk_get_rate(cpu_clk); + cpu_parent = clk_get_parent(cpu_clk); + hbus_rate = clk_get_rate(hbus_clk); + clk_set_parent(cpu_clk, osc_clk); + } else + pr_err("fail to get cpu clk\n"); + if (cpu_rate == 261818000) + clk_set_rate(hbus_clk, 8727267); + local_fiq_disable(); + + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + reg_clkctrl_clkseq = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_CLKSEQ); + + reg_clkctrl_xtal = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); + + + /* do suspend */ + mx28_cpu_standby_ptr = iram_virtual_addr; + + mx28_cpu_standby_ptr(); + + wakeupirq = __raw_readl(IO_ADDRESS(ICOLL_PHYS_ADDR) + HW_ICOLL_STAT); + + pr_info("wakeup irq = %d\n", wakeupirq); + + __raw_writel(reg_clkctrl_clkseq, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); + __raw_writel(reg_clkctrl_xtal, REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); + saved_sleep_state = 0; /* waking from standby */ + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + local_fiq_enable(); + + if (cpu_parent) { + clk_set_parent(cpu_clk, cpu_parent); + clk_set_rate(cpu_clk, cpu_rate); + clk_set_rate(hbus_clk, hbus_rate); + } + + clk_put(hbus_clk); + clk_put(pll_clk); + clk_put(osc_clk); + clk_put(cpu_clk); + + iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE); + mx28evk_enet_io_lowerpower_exit(); +} + +static noinline void do_mem(void) +{ + /* TODO */ +} + +static int mx28_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + do_standby(); + break; + case PM_SUSPEND_MEM: + do_mem(); + break; + } + return 0; +} + +static int mx28_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || + (state == PM_SUSPEND_MEM); +} + +static suspend_state_t saved_state; + +static int mx28_pm_begin(suspend_state_t state) +{ + saved_state = state; + return 0; +} + +static void mx28_pm_recover(void) +{ + /* + * The PSWITCH interrupt is enabled at do_standby, if the deivce + * suspend failed, the enable operation will not be executed, in that + * case, the POWER key will not be active again. + */ + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); +} + +static void mx28_pm_end(void) +{ + /*XXX: Nothing to do */ +} + +suspend_state_t mx28_pm_get_target(void) +{ + return saved_state; +} +EXPORT_SYMBOL(mx28_pm_get_target); + +/** + * mx28_pm_get_sleep_state - get sleep state we waking from + * + * returns boolean: 0 if waking up from standby, 1 otherwise + */ +int mx28_pm_sleep_was_deep(void) +{ + return saved_sleep_state; +} +EXPORT_SYMBOL(mx28_pm_sleep_was_deep); + +static struct platform_suspend_ops mx28_suspend_ops = { + .enter = mx28_pm_enter, + .valid = mx28_pm_valid, + .begin = mx28_pm_begin, + .end = mx28_pm_end, + .recover = mx28_pm_recover, +}; + +void mx28_pm_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + if (need_resched()) { + local_fiq_enable(); + local_irq_enable(); + return; + } + + __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, + REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_SET); + __asm__ __volatile__ ("mcr p15, 0, r0, c7, c0, 4"); + + local_fiq_enable(); + local_irq_enable(); +} + +static void mx28_pm_power_off(void) +{ + __raw_writel(BF_POWER_RESET_UNLOCK(0x3e77) | BM_POWER_RESET_PWD, + REGS_POWER_BASE + HW_POWER_RESET); +} + +struct mx28_pswitch_state { + int dev_running; +}; + +static DECLARE_COMPLETION(suspend_request); + +static int suspend_thread_fn(void *data) +{ + while (1) { + wait_for_completion_interruptible(&suspend_request); + pm_suspend(PM_SUSPEND_STANDBY); + } + return 0; +} + +static struct mx28_pswitch_state pswitch_state = { + .dev_running = 0, +}; + +#define PSWITCH_POWER_DOWN_DELAY 30 +static struct delayed_work pswitch_work; +static void pswitch_check_work(struct work_struct *work) +{ + int pin_value, i; + for (i = 0; i < PSWITCH_POWER_DOWN_DELAY; i++) { + pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BF_POWER_STS_PSWITCH(0x1); + if (pin_value == 0) + break; + msleep(100); + } + if (i < PSWITCH_POWER_DOWN_DELAY) { + pr_info("pswitch goto suspend\n"); + complete(&suspend_request); + } else { + pr_info("release pswitch to power down\n"); + for (i = 0; i < 500; i++) { + pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) + & BF_POWER_STS_PSWITCH(0x1); + if (pin_value == 0) + break; + msleep(10); + } + pr_info("pswitch power down\n"); + mx28_pm_power_off(); + } + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); +} + + +static irqreturn_t pswitch_interrupt(int irq, void *dev) +{ + + /* check if irq by pswitch */ + if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_PSWITCH_IRQ)) + return IRQ_HANDLED; + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + schedule_delayed_work(&pswitch_work, 1); + return IRQ_HANDLED; +} + +static struct irqaction pswitch_irq = { + .name = "pswitch", + .flags = IRQF_DISABLED | IRQF_SHARED, + .handler = pswitch_interrupt, + .dev_id = &pswitch_state, +}; + +static void init_pswitch(void) +{ + INIT_DELAYED_WORK(&pswitch_work, pswitch_check_work); + kthread_run(suspend_thread_fn, NULL, "pswitch"); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_POLARITY_PSWITCH | + BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + setup_irq(IRQ_VDD5V, &pswitch_irq); +} + +static int __init mx28_pm_init(void) +{ + saved_sram = kmalloc(0x4000, GFP_ATOMIC); + if (!saved_sram) { + printk(KERN_ERR + "PM Suspend: can't allocate memory to save portion of SRAM\n"); + return -ENOMEM; + } + + pm_power_off = mx28_pm_power_off; + pm_idle = mx28_pm_idle; + suspend_set_ops(&mx28_suspend_ops); + init_pswitch(); + return 0; +} + +late_initcall(mx28_pm_init); diff --git a/arch/arm/mach-mx28/power.c b/arch/arm/mach-mx28/power.c new file mode 100644 index 000000000000..3ea9161ea95d --- /dev/null +++ b/arch/arm/mach-mx28/power.c @@ -0,0 +1,582 @@ +/* + * Freescale STMP378X voltage regulator low-level driver + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* #define DEBUG */ + +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/gpio.h> + +#include "mx28_pins.h" +#include <mach/power.h> +#include <mach/regulator.h> +#include <mach/regs-power.h> + +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX) +#define MX28EVK_VBUS5v 5 + +static int get_voltage(struct mxs_regulator *sreg) +{ + int uv; + struct mxs_platform_regulator_data *rdata = sreg->rdata; + u32 val = __raw_readl(rdata->control_reg) & 0x1f; + if (sreg->rdata->control_reg == + (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)) { + if (val > 0x10) + val = 0x10; + uv = rdata->min_voltage + val * 50000; + pr_info("vddio = %d, val=%u\n", uv, val); + } else + uv = rdata->min_voltage + val * + (rdata->max_voltage - rdata->min_voltage) / 0x1f; + return uv; +} + +static int get_bo_voltage(struct mxs_regulator *sreg) +{ + int uv; + int offs; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700) >> 8; + return uv - 25000*offs; +} + +static int set_voltage(struct mxs_regulator *sreg, int uv) +{ + u32 val, reg, i; + + pr_debug("%s: uv %d, min %d, max %d\n", __func__, + uv, sreg->rdata->min_voltage, sreg->rdata->max_voltage); + + if (uv < sreg->rdata->min_voltage || uv > sreg->rdata->max_voltage) + return -EINVAL; + + if (sreg->rdata->control_reg == + (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)) + val = (uv - sreg->rdata->min_voltage) / 50000; + else + val = (uv - sreg->rdata->min_voltage) * 0x1f / + (sreg->rdata->max_voltage - sreg->rdata->min_voltage); + reg = (__raw_readl(sreg->rdata->control_reg) & ~0x1f); + pr_debug("%s: calculated val %d\n", __func__, val); + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 20; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int set_bo_voltage(struct mxs_regulator *sreg, int bo_uv) +{ + int uv; + int offs; + u32 reg; + int i; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (uv - bo_uv) / 25000; + if (offs < 0 || offs > 7) + return -EINVAL; + + reg = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700); + pr_debug("%s: calculated offs %d\n", __func__, offs); + __raw_writel((offs << 8) | reg, sreg->parent->rdata->control_reg); + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int enable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + u32 val; + + switch (mode) { + case REGULATOR_MODE_FAST: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val | (1 << 17), sreg->rdata->control_reg); + break; + + case REGULATOR_MODE_NORMAL: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val & ~(1<<17), sreg->rdata->control_reg); + break; + + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int get_mode(struct mxs_regulator *sreg) +{ + u32 val = __raw_readl(sreg->rdata->control_reg) & (1 << 17); + + return val ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; +} + +static struct mxs_platform_regulator_data vddd_data = { + .name = "vddd", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDDCTRL), + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdddbo_data = { + .name = "vddd_bo", + .parent_name = "vddd", + .set_voltage = set_bo_voltage, + .get_voltage = get_bo_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdda_data = { + .name = "vdda", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDACTRL), + .min_voltage = 1500000, + .max_voltage = 2275000, +}; + +#define MX28EVK_VDDIO_OFFSET 80000 +static struct mxs_platform_regulator_data vddio_data = { + .name = "vddio", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL), + .min_voltage = 2800000 + MX28EVK_VDDIO_OFFSET, + .max_voltage = 3600000 + MX28EVK_VDDIO_OFFSET, +}; + +static struct regulator_init_data vddd_init = { + .constraints = { + .name = "vddd", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +static struct regulator_init_data vdddbo_init = { + .constraints = { + .name = "vdddbo", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vdda_init = { + .constraints = { + .name = "vdda", + .min_uV = 1500000, + .max_uV = 2275000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vddio_init = { + .constraints = { + .name = "vddio", + .min_uV = 2800000 + MX28EVK_VDDIO_OFFSET, + .max_uV = 3600000 + MX28EVK_VDDIO_OFFSET, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +static int vbus5v_enable(struct mxs_regulator *sreg) +{ + gpio_set_value(USB_POWER_ENABLE, 1); + return 0; +} + +static int vbus5v_disable(struct mxs_regulator *sreg) +{ + gpio_set_value(USB_POWER_ENABLE, 0); + return 0; +} + +static int vbus5v_is_enabled(struct mxs_regulator *sreg) +{ + return gpio_get_value(USB_POWER_ENABLE); +} + + +static struct mxs_platform_regulator_data vbus5v_data = { + .name = "vbus5v", + .enable = vbus5v_enable, + .disable = vbus5v_disable, + .is_enabled = vbus5v_is_enabled, +}; + +static struct regulator_init_data vbus5v_init = { + .constraints = { + .name = "vbus5v", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + + +/* now the current regulators */ +/* Restriction: .... no set_current call on root regulator */ +static int main_add_current(struct mxs_regulator *sreg, + int uA) +{ + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + if (uA > 0 && (sreg->cur_current + uA > sreg->rdata->max_current)) + return -EINVAL; + else + sreg->cur_current += uA; + return 0; +} + +static int cur_reg_set_current(struct mxs_regulator *sreg, int uA) +{ + int ret = 0; + unsigned long flags; + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + + if (sreg->parent) { + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } + + + if ((!ret) || (!sreg->parent)) + goto out; + + if (sreg->mode == REGULATOR_MODE_FAST) + return ret; + + while (ret) { + wait_event(sreg->parent->wait_q , + (uA - sreg->cur_current < + sreg->parent->rdata->max_current - + sreg->parent->cur_current)); + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } +out: + if (sreg->parent && (uA - sreg->cur_current < 0)) + wake_up_all(&sreg->parent->wait_q); + sreg->cur_current = uA; + return 0; + +} + +static int cur_reg_get_current(struct mxs_regulator *sreg) +{ + return sreg->cur_current; +} + +static int enable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int cur_reg_is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int cur_reg_set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + case REGULATOR_MODE_FAST: + sreg->mode = mode; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int cur_reg_get_mode(struct mxs_regulator *sreg) +{ + return sreg->mode; +} + +static struct mxs_platform_regulator_data overall_cur_data = { + .name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, + .max_current = 0x7fffffff, +}; + +static struct regulator_init_data overall_cur_init = { + .constraints = { + .name = "overall_current", + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_FAST, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | + REGULATOR_CHANGE_MODE, + .max_uA = 0x7fffffff, + .min_uA = 0x0, + .always_on = 1, + } +}; + +static struct mxs_platform_regulator_data sibling_cur_data = { + .parent_name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, +}; + + +static const char *device_names[] = { + "mxs-duart", "mxs-bl", "mxs-i2c" +}; + +static int sibling_current_devices_num; + +int mxs_platform_add_regulator(const char *name, int count) +{ + int i; + pr_debug("%s: name %s, count %d\n", __func__, name, count); + for (i = sibling_current_devices_num; + i < sibling_current_devices_num + count; + i++) { + struct regulator_init_data *sibling_init = + kzalloc(sizeof(struct regulator_init_data), + GFP_KERNEL); + struct mxs_regulator *curr_reg = + kzalloc(sizeof(struct mxs_regulator), + GFP_KERNEL); + struct mxs_platform_regulator_data *d = + kzalloc(sizeof(struct mxs_platform_regulator_data), + GFP_KERNEL); + if (!d || !curr_reg || !sibling_init) + return -ENOMEM; + + sibling_init->constraints.valid_modes_mask = + REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST; + sibling_init->constraints.valid_ops_mask = + REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_MODE; + sibling_init->constraints.max_uA = 0x7fffffff; + sibling_init->constraints.min_uA = 0x0; + + memcpy(d, &sibling_cur_data, sizeof(sibling_cur_data)); + d->parent_name = kstrdup(sibling_cur_data.parent_name, + GFP_KERNEL); + snprintf(d->name, 80, "%s-%d", + name, i - sibling_current_devices_num + 1); + sibling_init->constraints.name = kstrdup(d->name, GFP_KERNEL); + sibling_init->constraints.always_on = 1; + curr_reg->rdata = d; + mxs_register_regulator(curr_reg, 101 + i, sibling_init); + } + sibling_current_devices_num += count; + return 0; +} + +static struct mxs_regulator vddd_reg = { + .rdata = &vddd_data, +}; + +static struct mxs_regulator vdda_reg = { + .rdata = &vdda_data, +}; + +static struct mxs_regulator vddio_reg = { + .rdata = &vddio_data, +}; + +static struct mxs_regulator vdddbo_reg = { + .rdata = &vdddbo_data, +}; + +static struct mxs_regulator overall_cur_reg = { + .rdata = &overall_cur_data, +}; + +static struct mxs_regulator vbus5v_reg = { + .rdata = &vbus5v_data, +}; + +static int __init regulators_init(void) +{ + int i; + int retval = 0; + u32 vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) & ~0x1f; + pr_debug("regulators_init \n"); + __raw_writel(vddio | 0xA, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + vdddbo_reg.parent = &vddd_reg; + mxs_register_regulator(&vddd_reg, MXS_VDDD, &vddd_init); + mxs_register_regulator(&vdddbo_reg, MXS_VDDDBO, &vdddbo_init); + mxs_register_regulator(&vdda_reg, MXS_VDDA, &vdda_init); + mxs_register_regulator(&vddio_reg, MXS_VDDIO, &vddio_init); + mxs_register_regulator(&overall_cur_reg, + MXS_OVERALL_CUR, &overall_cur_init); + + mxs_register_regulator(&vbus5v_reg, MX28EVK_VBUS5v, &vbus5v_init); + + for (i = 0; i < ARRAY_SIZE(device_names); i++) { + retval = mxs_platform_add_regulator(device_names[i], 1); + if (retval) + return retval; + } + mxs_platform_add_regulator("mmc_ssp", 2); + mxs_platform_add_regulator("charger", 1); + mxs_platform_add_regulator("power-test", 1); + mxs_platform_add_regulator("cpufreq", 1); + gpio_direction_output(USB_POWER_ENABLE, 0); + return 0; +} +postcore_initcall(regulators_init); diff --git a/arch/arm/mach-mx28/regs-clkctrl.h b/arch/arm/mach-mx28/regs-clkctrl.h new file mode 100644 index 000000000000..161860c2fcf0 --- /dev/null +++ b/arch/arm/mach-mx28/regs-clkctrl.h @@ -0,0 +1,634 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + +#define HW_CLKCTRL_PLL0CTRL0 (0x00000000) +#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) +#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) + +#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL1CTRL0 (0x00000020) +#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) +#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) +#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) + +#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 +#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) + +#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL2CTRL0 (0x00000040) +#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) +#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) +#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) + +#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 +#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) +#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 +#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 +#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) +#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 +#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF +#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) + +#define HW_CLKCTRL_CPU (0x00000050) +#define HW_CLKCTRL_CPU_SET (0x00000054) +#define HW_CLKCTRL_CPU_CLR (0x00000058) +#define HW_CLKCTRL_CPU_TOG (0x0000005c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000060) +#define HW_CLKCTRL_HBUS_SET (0x00000064) +#define HW_CLKCTRL_HBUS_CLR (0x00000068) +#define HW_CLKCTRL_HBUS_TOG (0x0000006c) + +#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 +#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 +#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000070) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 12 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000080) +#define HW_CLKCTRL_XTAL_SET (0x00000084) +#define HW_CLKCTRL_XTAL_CLR (0x00000088) +#define HW_CLKCTRL_XTAL_TOG (0x0000008c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BP_CLKCTRL_XTAL_RSRVD2 27 +#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 +#define BF_CLKCTRL_XTAL_RSRVD2(v) \ + (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_SSP0 (0x00000090) + +#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP0_BUSY 0x20000000 +#define BP_CLKCTRL_SSP0_RSRVD1 10 +#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP0_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) +#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP0_DIV 0 +#define BM_CLKCTRL_SSP0_DIV 0x000001FF +#define BF_CLKCTRL_SSP0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP0_DIV) + +#define HW_CLKCTRL_SSP1 (0x000000a0) + +#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP1_BUSY 0x20000000 +#define BP_CLKCTRL_SSP1_RSRVD1 10 +#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP1_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) +#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP1_DIV 0 +#define BM_CLKCTRL_SSP1_DIV 0x000001FF +#define BF_CLKCTRL_SSP1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP1_DIV) + +#define HW_CLKCTRL_SSP2 (0x000000b0) + +#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP2_BUSY 0x20000000 +#define BP_CLKCTRL_SSP2_RSRVD1 10 +#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP2_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) +#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP2_DIV 0 +#define BM_CLKCTRL_SSP2_DIV 0x000001FF +#define BF_CLKCTRL_SSP2_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP2_DIV) + +#define HW_CLKCTRL_SSP3 (0x000000c0) + +#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP3_BUSY 0x20000000 +#define BP_CLKCTRL_SSP3_RSRVD1 10 +#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP3_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) +#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP3_DIV 0 +#define BM_CLKCTRL_SSP3_DIV 0x000001FF +#define BF_CLKCTRL_SSP3_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP3_DIV) + +#define HW_CLKCTRL_GPMI (0x000000d0) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x000000e0) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000f0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_SAIF0 (0x00000100) + +#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF0_RSRVD1 17 +#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) +#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF0_DIV 0 +#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) + +#define HW_CLKCTRL_SAIF1 (0x00000110) + +#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF1_RSRVD1 17 +#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) +#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF1_DIV 0 +#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) + +#define HW_CLKCTRL_DIS_LCDIF (0x00000120) + +#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 +#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 +#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ + (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) +#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 +#define BP_CLKCTRL_DIS_LCDIF_DIV 0 +#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF +#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) + +#define HW_CLKCTRL_ETM (0x00000130) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 8 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000007F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_ENET (0x00000140) + +#define BM_CLKCTRL_ENET_SLEEP 0x80000000 +#define BM_CLKCTRL_ENET_DISABLE 0x40000000 +#define BM_CLKCTRL_ENET_STATUS 0x20000000 +#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 +#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 +#define BP_CLKCTRL_ENET_DIV_TIME 21 +#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 +#define BF_CLKCTRL_ENET_DIV_TIME(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) +#define BP_CLKCTRL_ENET_TIME_SEL 19 +#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 +#define BF_CLKCTRL_ENET_TIME_SEL(v) \ + (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) +#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 +#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 +#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 +#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 +#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 +#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 +#define BP_CLKCTRL_ENET_RSRVD0 0 +#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF +#define BF_CLKCTRL_ENET_RSRVD0(v) \ + (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) + +#define HW_CLKCTRL_HSADC (0x00000150) + +#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 +#define BM_CLKCTRL_HSADC_RESETB 0x40000000 +#define BP_CLKCTRL_HSADC_FREQDIV 28 +#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 +#define BF_CLKCTRL_HSADC_FREQDIV(v) \ + (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) +#define BP_CLKCTRL_HSADC_RSRVD1 0 +#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF +#define BF_CLKCTRL_HSADC_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) + +#define HW_CLKCTRL_FLEXCAN (0x00000160) + +#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 +#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 +#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 +#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 +#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF +#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) + +#define HW_CLKCTRL_FRAC0 (0x000001b0) +#define HW_CLKCTRL_FRAC0_SET (0x000001b4) +#define HW_CLKCTRL_FRAC0_CLR (0x000001b8) +#define HW_CLKCTRL_FRAC0_TOG (0x000001bc) + +#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 +#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC0_IO0FRAC 24 +#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 +#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 +#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC0_IO1FRAC 16 +#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 +#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC0_EMIFRAC 8 +#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) +#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC0_CPUFRAC 0 +#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x000001c0) +#define HW_CLKCTRL_FRAC1_SET (0x000001c4) +#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) +#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) + +#define BP_CLKCTRL_FRAC1_RSRVD2 24 +#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 +#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) +#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 +#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC1_GPMIFRAC 16 +#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 +#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC1_HSADCFRAC 8 +#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 +#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC1_PIXFRAC 0 +#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F +#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) + +#define HW_CLKCTRL_CLKSEQ (0x000001d0) +#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) +#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) +#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) + +#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ + (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 +#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 +#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 +#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 + +#define HW_CLKCTRL_RESET (0x000001e0) + +#define BP_CLKCTRL_RESET_RSRVD 6 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 +#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 +#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 +#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x000001f0) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000200) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-mx28/regs-digctl.h b/arch/arm/mach-mx28/regs-digctl.h new file mode 100644 index 000000000000..6ebda07581c2 --- /dev/null +++ b/arch/arm/mach-mx28/regs-digctl.h @@ -0,0 +1,1022 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM___DIGCTL_H +#define __ARCH_ARM___DIGCTL_H + + +#define HW_DIGCTL_CTRL (0x00000000) +#define HW_DIGCTL_CTRL_SET (0x00000004) +#define HW_DIGCTL_CTRL_CLR (0x00000008) +#define HW_DIGCTL_CTRL_TOG (0x0000000c) + +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BP_DIGCTL_CTRL_RSVD2 25 +#define BM_DIGCTL_CTRL_RSVD2 0x3E000000 +#define BF_DIGCTL_CTRL_RSVD2(v) \ + (((v) << 25) & BM_DIGCTL_CTRL_RSVD2) +#define BM_DIGCTL_CTRL_USB1_OVERCURRENT_ENABLE 0x01000000 +#define BM_DIGCTL_CTRL_USB0_OVERCURRENT_ENABLE 0x00800000 +#define BM_DIGCTL_CTRL_USB1_OVERCURRENT_POL 0x00400000 +#define BM_DIGCTL_CTRL_USB0_OVERCURRENT_POL 0x00200000 +#define BM_DIGCTL_CTRL_USB1_TESTMODE 0x00100000 +#define BM_DIGCTL_CTRL_USB0_TESTMODE 0x00080000 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00040000 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00020000 +#define BM_DIGCTL_CTRL_USB1_CLKGATE 0x00010000 +#define BV_DIGCTL_CTRL_USB1_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB1_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_DUART_LOOPBACK 0x00004000 +#define BV_DIGCTL_CTRL_DUART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_DUART_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_AUART01_LOOPBACK 0x00002000 +#define BV_DIGCTL_CTRL_AUART01_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_AUART01_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_RSVD1 0x00001000 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 10 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00000C00 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \ + (((v) << 10) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL) +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__DIRECT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CROSSINPUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CLKSRCSAIF0PIN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CLKSRCSAIF1PIN 0x3 +#define BP_DIGCTL_CTRL_RSVD0 4 +#define BM_DIGCTL_CTRL_RSVD0 0x000003F0 +#define BF_DIGCTL_CTRL_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_CTRL_RSVD0) +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008 +#define BM_DIGCTL_CTRL_USB0_CLKGATE 0x00000004 +#define BV_DIGCTL_CTRL_USB0_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB0_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001 + +#define HW_DIGCTL_STATUS (0x00000010) +#define HW_DIGCTL_STATUS_SET (0x00000014) +#define HW_DIGCTL_STATUS_CLR (0x00000018) +#define HW_DIGCTL_STATUS_TOG (0x0000001c) + +#define BM_DIGCTL_STATUS_USB0_HS_PRESENT 0x80000000 +#define BM_DIGCTL_STATUS_USB0_OTG_PRESENT 0x40000000 +#define BM_DIGCTL_STATUS_USB0_HOST_PRESENT 0x20000000 +#define BM_DIGCTL_STATUS_USB0_DEVICE_PRESENT 0x10000000 +#define BM_DIGCTL_STATUS_USB1_HS_PRESENT 0x08000000 +#define BM_DIGCTL_STATUS_USB1_OTG_PRESENT 0x04000000 +#define BM_DIGCTL_STATUS_USB1_HOST_PRESENT 0x02000000 +#define BM_DIGCTL_STATUS_USB1_DEVICE_PRESENT 0x01000000 +#define BP_DIGCTL_STATUS_RSVD0 5 +#define BM_DIGCTL_STATUS_RSVD0 0x00FFFFE0 +#define BF_DIGCTL_STATUS_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_STATUS_RSVD0) +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010 +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \ + (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE) +#define BM_DIGCTL_STATUS_WRITTEN 0x00000001 + +#define HW_DIGCTL_HCLKCOUNT (0x00000020) +#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024) +#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028) +#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c) + +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v) + +#define HW_DIGCTL_RAMCTRL (0x00000030) +#define HW_DIGCTL_RAMCTRL_SET (0x00000034) +#define HW_DIGCTL_RAMCTRL_CLR (0x00000038) +#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c) + +#define BP_DIGCTL_RAMCTRL_RSVD1 15 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFF8000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) \ + (((v) << 15) & BM_DIGCTL_RAMCTRL_RSVD1) +#define BM_DIGCTL_RAMCTRL_TBYPASS 0x00004000 +#define BM_DIGCTL_RAMCTRL_DEBUG_ENABLE 0x00002000 +#define BP_DIGCTL_RAMCTRL_DEBUG_CODE 8 +#define BM_DIGCTL_RAMCTRL_DEBUG_CODE 0x00001F00 +#define BF_DIGCTL_RAMCTRL_DEBUG_CODE(v) \ + (((v) << 8) & BM_DIGCTL_RAMCTRL_DEBUG_CODE) +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY1 0x4 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY2 0x5 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY3 0x6 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY4 0x7 +#define BP_DIGCTL_RAMCTRL_RSVD0 0 +#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FF +#define BF_DIGCTL_RAMCTRL_RSVD0(v) \ + (((v) << 0) & BM_DIGCTL_RAMCTRL_RSVD0) + +#define HW_DIGCTL_EMI_STATUS (0x00000040) +#define HW_DIGCTL_EMI_STATUS_SET (0x00000044) +#define HW_DIGCTL_EMI_STATUS_CLR (0x00000048) +#define HW_DIGCTL_EMI_STATUS_TOG (0x0000004c) + +#define BP_DIGCTL_EMI_STATUS_RSVD0 5 +#define BM_DIGCTL_EMI_STATUS_RSVD0 0xFFFFFFE0 +#define BF_DIGCTL_EMI_STATUS_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_EMI_STATUS_RSVD0) +#define BP_DIGCTL_EMI_STATUS_POWER_MODE 0 +#define BM_DIGCTL_EMI_STATUS_POWER_MODE 0x0000001F +#define BF_DIGCTL_EMI_STATUS_POWER_MODE(v) \ + (((v) << 0) & BM_DIGCTL_EMI_STATUS_POWER_MODE) +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM5 0x1 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM4 0x2 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM3 0x4 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM2 0x8 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM1 0x10 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__NORMAL 0x0 + +#define HW_DIGCTL_READ_MARGIN (0x00000050) +#define HW_DIGCTL_READ_MARGIN_SET (0x00000054) +#define HW_DIGCTL_READ_MARGIN_CLR (0x00000058) +#define HW_DIGCTL_READ_MARGIN_TOG (0x0000005c) + +#define BP_DIGCTL_READ_MARGIN_RSVD0 4 +#define BM_DIGCTL_READ_MARGIN_RSVD0 0xFFFFFFF0 +#define BF_DIGCTL_READ_MARGIN_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_READ_MARGIN_RSVD0) +#define BP_DIGCTL_READ_MARGIN_ROM 0 +#define BM_DIGCTL_READ_MARGIN_ROM 0x0000000F +#define BF_DIGCTL_READ_MARGIN_ROM(v) \ + (((v) << 0) & BM_DIGCTL_READ_MARGIN_ROM) + +#define HW_DIGCTL_WRITEONCE (0x00000060) + +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF +#define BF_DIGCTL_WRITEONCE_BITS(v) (v) + +#define HW_DIGCTL_BIST_CTL (0x00000070) +#define HW_DIGCTL_BIST_CTL_SET (0x00000074) +#define HW_DIGCTL_BIST_CTL_CLR (0x00000078) +#define HW_DIGCTL_BIST_CTL_TOG (0x0000007c) + +#define BM_DIGCTL_BIST_CTL_BIST_TESTMODE 0x80000000 +#define BM_DIGCTL_BIST_CTL_BIST_RESETN 0x40000000 +#define BM_DIGCTL_BIST_CTL_BIST_DEBUGZ 0x20000000 +#define BM_DIGCTL_BIST_CTL_BIST_CHECKB 0x10000000 +#define BM_DIGCTL_BIST_CTL_BIST_RESUME 0x08000000 +#define BP_DIGCTL_BIST_CTL_RSVD0 15 +#define BM_DIGCTL_BIST_CTL_RSVD0 0x07FF8000 +#define BF_DIGCTL_BIST_CTL_RSVD0(v) \ + (((v) << 15) & BM_DIGCTL_BIST_CTL_RSVD0) +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_RETENTION 0x00004000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_PASS 0x00002000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_FAIL 0x00001000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_DONE 0x00000800 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_START 0x00000400 +#define BM_DIGCTL_BIST_CTL_PXP_BIST_START 0x00000200 +#define BM_DIGCTL_BIST_CTL_LCDIF_BIST_START 0x00000100 +#define BM_DIGCTL_BIST_CTL_DCP_BIST_START 0x00000080 +#define BM_DIGCTL_BIST_CTL_ENET_BIST_START 0x00000040 +#define BM_DIGCTL_BIST_CTL_USB1_BIST_START 0x00000020 +#define BM_DIGCTL_BIST_CTL_USB0_BIST_START 0x00000010 +#define BM_DIGCTL_BIST_CTL_DMA1_BIST_START 0x00000008 +#define BM_DIGCTL_BIST_CTL_DMA0_BIST_START 0x00000004 +#define BM_DIGCTL_BIST_CTL_CACHE_BIST_START 0x00000002 +#define BM_DIGCTL_BIST_CTL_CAN_BIST_START 0x00000001 + +#define HW_DIGCTL_BIST_STATUS (0x00000080) +#define HW_DIGCTL_BIST_STATUS_SET (0x00000084) +#define HW_DIGCTL_BIST_STATUS_CLR (0x00000088) +#define HW_DIGCTL_BIST_STATUS_TOG (0x0000008c) + +#define BP_DIGCTL_BIST_STATUS_RSVD0 30 +#define BM_DIGCTL_BIST_STATUS_RSVD0 0xC0000000 +#define BF_DIGCTL_BIST_STATUS_RSVD0(v) \ + (((v) << 30) & BM_DIGCTL_BIST_STATUS_RSVD0) +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_RETENTION 0x20000000 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_RETENTION 0x10000000 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_RETENTION 0x08000000 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_RETENTION 0x04000000 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_RETENTION 0x02000000 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_RETENTION 0x01000000 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_RETENTION 0x00800000 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_RETENTION 0x00400000 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_RETENTION 0x00200000 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_RETENTION 0x00100000 +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_FAIL 0x00080000 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_FAIL 0x00040000 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_FAIL 0x00020000 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_FAIL 0x00010000 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_FAIL 0x00008000 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_FAIL 0x00004000 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_FAIL 0x00002000 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_FAIL 0x00001000 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_FAIL 0x00000800 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_FAIL 0x00000400 +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_DONE 0x00000200 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_DONE 0x00000100 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_DONE 0x00000080 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_DONE 0x00000040 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_DONE 0x00000020 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_DONE 0x00000010 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_DONE 0x00000008 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_DONE 0x00000004 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_DONE 0x00000002 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_DONE 0x00000001 + +#define HW_DIGCTL_ENTROPY (0x00000090) + +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_VALUE(v) (v) + +#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0) + +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v) + +#define HW_DIGCTL_MICROSECONDS (0x000000c0) +#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4) +#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8) +#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc) + +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v) + +#define HW_DIGCTL_DBGRD (0x000000d0) + +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v) + +#define HW_DIGCTL_DBG (0x000000e0) + +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF +#define BF_DIGCTL_DBG_VALUE(v) (v) + +#define HW_DIGCTL_USB_LOOPBACK (0x00000100) +#define HW_DIGCTL_USB_LOOPBACK_SET (0x00000104) +#define HW_DIGCTL_USB_LOOPBACK_CLR (0x00000108) +#define HW_DIGCTL_USB_LOOPBACK_TOG (0x0000010c) + +#define BP_DIGCTL_USB_LOOPBACK_RSVD0 18 +#define BM_DIGCTL_USB_LOOPBACK_RSVD0 0xFFFC0000 +#define BF_DIGCTL_USB_LOOPBACK_RSVD0(v) \ + (((v) << 18) & BM_DIGCTL_USB_LOOPBACK_RSVD0) +#define BM_DIGCTL_USB_LOOPBACK_USB1_TST_START 0x00020000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_LS 0x00010000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_HS 0x00008000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_EN 0x00004000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_HIZ 0x00002000 +#define BM_DIGCTL_USB_LOOPBACK_UTMI1_DIG_TST1 0x00001000 +#define BM_DIGCTL_USB_LOOPBACK_UTMI1_DIG_TST0 0x00000800 +#define BM_DIGCTL_USB_LOOPBACK_USB0_TST_START 0x00000400 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_LS 0x00000200 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_HS 0x00000100 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_EN 0x00000080 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_HIZ 0x00000040 +#define BM_DIGCTL_USB_LOOPBACK_UTMI0_DIG_TST1 0x00000020 +#define BM_DIGCTL_USB_LOOPBACK_UTMI0_DIG_TST0 0x00000010 +#define BM_DIGCTL_USB_LOOPBACK_UTMO1_DIG_TST1 0x00000008 +#define BM_DIGCTL_USB_LOOPBACK_UTMO1_DIG_TST0 0x00000004 +#define BM_DIGCTL_USB_LOOPBACK_UTMO0_DIG_TST1 0x00000002 +#define BM_DIGCTL_USB_LOOPBACK_UTMO0_DIG_TST0 0x00000001 + +#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110) +#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114) +#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118) +#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c) + +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120) +#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124) +#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128) +#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c) + +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130) +#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134) +#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138) +#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c) + +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140) +#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144) +#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148) +#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c) + +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150) +#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154) +#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158) +#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c) + +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160) +#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164) +#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168) +#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c) + +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170) +#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174) +#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178) +#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c) + +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180) +#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184) +#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188) +#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c) + +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190) +#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194) +#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198) +#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c) + +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00) + +#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0) +#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4) +#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8) +#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac) + +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10) + +#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0) +#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4) +#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8) +#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc) + +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20) + +#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0) +#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4) +#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8) +#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc) + +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30) + +#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0) +#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4) +#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8) +#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc) + +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0x80000000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x7F000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00800000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x007F0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x00008000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00007F00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x00000080 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000007F +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00) + +#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0) +#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4) +#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8) +#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec) + +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0x80000000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x7F000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00800000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x007F0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x00008000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00007F00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x00000080 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000007F +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20) + +#define HW_DIGCTL_SCRATCH0 (0x00000280) + +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH0_PTR(v) (v) + +#define HW_DIGCTL_SCRATCH1 (0x00000290) + +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH1_PTR(v) (v) + +#define HW_DIGCTL_ARMCACHE (0x000002a0) + +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) \ + (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4) +#define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \ + (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS) +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) \ + (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3) +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \ + (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS) +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) \ + (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \ + (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS) +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) \ + (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \ + (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS) +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C +#define BF_DIGCTL_ARMCACHE_RSVD0(v) \ + (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \ + (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS) + +#define HW_DIGCTL_DEBUG_TRAP (0x000002b0) +#define HW_DIGCTL_DEBUG_TRAP_SET (0x000002b4) +#define HW_DIGCTL_DEBUG_TRAP_CLR (0x000002b8) +#define HW_DIGCTL_DEBUG_TRAP_TOG (0x000002bc) + +#define BP_DIGCTL_DEBUG_TRAP_RSVD2 12 +#define BM_DIGCTL_DEBUG_TRAP_RSVD2 0xFFFFF000 +#define BF_DIGCTL_DEBUG_TRAP_RSVD2(v) \ + (((v) << 12) & BM_DIGCTL_DEBUG_TRAP_RSVD2) +#define BP_DIGCTL_DEBUG_TRAP_RSVD1 10 +#define BM_DIGCTL_DEBUG_TRAP_RSVD1 0x00000C00 +#define BF_DIGCTL_DEBUG_TRAP_RSVD1(v) \ + (((v) << 10) & BM_DIGCTL_DEBUG_TRAP_RSVD1) +#define BP_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID 8 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID 0x00000300 +#define BF_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID(v) \ + (((v) << 8) & BM_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID) +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__PXP 0x0 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__LCDIF 0x1 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__BCH 0x2 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__DCP 0x3 +#define BM_DIGCTL_DEBUG_TRAP_RSVD0 0x00000080 +#define BP_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID 4 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID 0x00000070 +#define BF_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID(v) \ + (((v) << 4) & BM_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID) +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__APBH_BRIDE_DMA 0x0 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__APBX_BRIDE_DMA 0x1 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__USB0 0x2 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__USB1 0x3 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__ENET_M0 0x4 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__ENET_M1 0x5 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L3_IRQ 0x00000008 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L0_IRQ 0x00000004 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_IN_RANGE 0x00000002 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_ENABLE 0x00000001 + +#define HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW (0x000002c0) + +#define BP_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH (0x000002d0) + +#define BP_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW (0x000002e0) + +#define BP_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH (0x000002f0) + +#define BP_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_FSL (0x00000300) + +#define BP_DIGCTL_FSL_COPYRIGHT 0 +#define BM_DIGCTL_FSL_COPYRIGHT 0xFFFFFFFF +#define BF_DIGCTL_FSL_COPYRIGHT(v) (v) + +#define HW_DIGCTL_CHIPID (0x00000310) + +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \ + (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE) +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00 +#define BF_DIGCTL_CHIPID_RSVD0(v) \ + (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0x000000FF +#define BF_DIGCTL_CHIPID_REVISION(v) \ + (((v) << 0) & BM_DIGCTL_CHIPID_REVISION) + +#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330) + +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 24 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0xFF000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \ + (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0) +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x00FF0000 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \ + (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBHDMA 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBXDMA 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB0 0x4 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB1 0x8 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__UDMA0 0x10 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__UDMA1 0x20 +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x0000FF00 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARMD 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x000000FF +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \ + (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARMI 0x1 + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370) + +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380) + +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390) + +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0) + +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0) + +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0) + +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0) + +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0) + +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0) + +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_MPTE0_LOC (0x00000500) + +#define BM_DIGCTL_MPTE0_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE0_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE0_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE0_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE0_LOC_RSVD1) +#define BP_DIGCTL_MPTE0_LOC_SPAN 24 +#define BM_DIGCTL_MPTE0_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE0_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE0_LOC_SPAN) +#define BP_DIGCTL_MPTE0_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE0_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE0_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE0_LOC_RSVD0) +#define BP_DIGCTL_MPTE0_LOC_LOC 0 +#define BM_DIGCTL_MPTE0_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE0_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE0_LOC_LOC) + +#define HW_DIGCTL_MPTE1_LOC (0x00000510) + +#define BM_DIGCTL_MPTE1_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE1_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE1_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE1_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE1_LOC_RSVD1) +#define BP_DIGCTL_MPTE1_LOC_SPAN 24 +#define BM_DIGCTL_MPTE1_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE1_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE1_LOC_SPAN) +#define BP_DIGCTL_MPTE1_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE1_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE1_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE1_LOC_RSVD0) +#define BP_DIGCTL_MPTE1_LOC_LOC 0 +#define BM_DIGCTL_MPTE1_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE1_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE1_LOC_LOC) + +#define HW_DIGCTL_MPTE2_LOC (0x00000520) + +#define BM_DIGCTL_MPTE2_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE2_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE2_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE2_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE2_LOC_RSVD1) +#define BP_DIGCTL_MPTE2_LOC_SPAN 24 +#define BM_DIGCTL_MPTE2_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE2_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE2_LOC_SPAN) +#define BP_DIGCTL_MPTE2_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE2_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE2_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE2_LOC_RSVD0) +#define BP_DIGCTL_MPTE2_LOC_LOC 0 +#define BM_DIGCTL_MPTE2_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE2_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE2_LOC_LOC) + +#define HW_DIGCTL_MPTE3_LOC (0x00000530) + +#define BM_DIGCTL_MPTE3_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE3_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE3_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE3_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE3_LOC_RSVD1) +#define BP_DIGCTL_MPTE3_LOC_SPAN 24 +#define BM_DIGCTL_MPTE3_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE3_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE3_LOC_SPAN) +#define BP_DIGCTL_MPTE3_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE3_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE3_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE3_LOC_RSVD0) +#define BP_DIGCTL_MPTE3_LOC_LOC 0 +#define BM_DIGCTL_MPTE3_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE3_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE3_LOC_LOC) + +#define HW_DIGCTL_MPTE4_LOC (0x00000540) + +#define BM_DIGCTL_MPTE4_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE4_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE4_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE4_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE4_LOC_RSVD1) +#define BP_DIGCTL_MPTE4_LOC_SPAN 24 +#define BM_DIGCTL_MPTE4_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE4_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE4_LOC_SPAN) +#define BP_DIGCTL_MPTE4_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE4_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE4_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE4_LOC_RSVD0) +#define BP_DIGCTL_MPTE4_LOC_LOC 0 +#define BM_DIGCTL_MPTE4_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE4_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE4_LOC_LOC) + +#define HW_DIGCTL_MPTE5_LOC (0x00000550) + +#define BM_DIGCTL_MPTE5_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE5_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE5_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE5_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE5_LOC_RSVD1) +#define BP_DIGCTL_MPTE5_LOC_SPAN 24 +#define BM_DIGCTL_MPTE5_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE5_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE5_LOC_SPAN) +#define BP_DIGCTL_MPTE5_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE5_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE5_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE5_LOC_RSVD0) +#define BP_DIGCTL_MPTE5_LOC_LOC 0 +#define BM_DIGCTL_MPTE5_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE5_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE5_LOC_LOC) + +#define HW_DIGCTL_MPTE6_LOC (0x00000560) + +#define BM_DIGCTL_MPTE6_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE6_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE6_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE6_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE6_LOC_RSVD1) +#define BP_DIGCTL_MPTE6_LOC_SPAN 24 +#define BM_DIGCTL_MPTE6_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE6_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE6_LOC_SPAN) +#define BP_DIGCTL_MPTE6_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE6_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE6_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE6_LOC_RSVD0) +#define BP_DIGCTL_MPTE6_LOC_LOC 0 +#define BM_DIGCTL_MPTE6_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE6_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE6_LOC_LOC) + +#define HW_DIGCTL_MPTE7_LOC (0x00000570) + +#define BM_DIGCTL_MPTE7_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE7_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE7_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE7_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE7_LOC_RSVD1) +#define BP_DIGCTL_MPTE7_LOC_SPAN 24 +#define BM_DIGCTL_MPTE7_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE7_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE7_LOC_SPAN) +#define BP_DIGCTL_MPTE7_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE7_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE7_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE7_LOC_RSVD0) +#define BP_DIGCTL_MPTE7_LOC_LOC 0 +#define BM_DIGCTL_MPTE7_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE7_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE7_LOC_LOC) + +#define HW_DIGCTL_MPTE8_LOC (0x00000580) + +#define BM_DIGCTL_MPTE8_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE8_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE8_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE8_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE8_LOC_RSVD1) +#define BP_DIGCTL_MPTE8_LOC_SPAN 24 +#define BM_DIGCTL_MPTE8_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE8_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE8_LOC_SPAN) +#define BP_DIGCTL_MPTE8_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE8_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE8_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE8_LOC_RSVD0) +#define BP_DIGCTL_MPTE8_LOC_LOC 0 +#define BM_DIGCTL_MPTE8_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE8_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE8_LOC_LOC) + +#define HW_DIGCTL_MPTE9_LOC (0x00000590) + +#define BM_DIGCTL_MPTE9_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE9_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE9_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE9_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE9_LOC_RSVD1) +#define BP_DIGCTL_MPTE9_LOC_SPAN 24 +#define BM_DIGCTL_MPTE9_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE9_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE9_LOC_SPAN) +#define BP_DIGCTL_MPTE9_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE9_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE9_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE9_LOC_RSVD0) +#define BP_DIGCTL_MPTE9_LOC_LOC 0 +#define BM_DIGCTL_MPTE9_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE9_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE9_LOC_LOC) + +#define HW_DIGCTL_MPTE10_LOC (0x000005a0) + +#define BM_DIGCTL_MPTE10_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE10_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE10_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE10_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE10_LOC_RSVD1) +#define BP_DIGCTL_MPTE10_LOC_SPAN 24 +#define BM_DIGCTL_MPTE10_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE10_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE10_LOC_SPAN) +#define BP_DIGCTL_MPTE10_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE10_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE10_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE10_LOC_RSVD0) +#define BP_DIGCTL_MPTE10_LOC_LOC 0 +#define BM_DIGCTL_MPTE10_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE10_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE10_LOC_LOC) + +#define HW_DIGCTL_MPTE11_LOC (0x000005b0) + +#define BM_DIGCTL_MPTE11_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE11_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE11_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE11_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE11_LOC_RSVD1) +#define BP_DIGCTL_MPTE11_LOC_SPAN 24 +#define BM_DIGCTL_MPTE11_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE11_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE11_LOC_SPAN) +#define BP_DIGCTL_MPTE11_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE11_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE11_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE11_LOC_RSVD0) +#define BP_DIGCTL_MPTE11_LOC_LOC 0 +#define BM_DIGCTL_MPTE11_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE11_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE11_LOC_LOC) + +#define HW_DIGCTL_MPTE12_LOC (0x000005c0) + +#define BM_DIGCTL_MPTE12_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE12_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE12_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE12_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE12_LOC_RSVD1) +#define BP_DIGCTL_MPTE12_LOC_SPAN 24 +#define BM_DIGCTL_MPTE12_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE12_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE12_LOC_SPAN) +#define BP_DIGCTL_MPTE12_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE12_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE12_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE12_LOC_RSVD0) +#define BP_DIGCTL_MPTE12_LOC_LOC 0 +#define BM_DIGCTL_MPTE12_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE12_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE12_LOC_LOC) + +#define HW_DIGCTL_MPTE13_LOC (0x000005d0) + +#define BM_DIGCTL_MPTE13_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE13_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE13_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE13_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE13_LOC_RSVD1) +#define BP_DIGCTL_MPTE13_LOC_SPAN 24 +#define BM_DIGCTL_MPTE13_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE13_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE13_LOC_SPAN) +#define BP_DIGCTL_MPTE13_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE13_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE13_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE13_LOC_RSVD0) +#define BP_DIGCTL_MPTE13_LOC_LOC 0 +#define BM_DIGCTL_MPTE13_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE13_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE13_LOC_LOC) + +#define HW_DIGCTL_MPTE14_LOC (0x000005e0) + +#define BM_DIGCTL_MPTE14_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE14_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE14_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE14_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE14_LOC_RSVD1) +#define BP_DIGCTL_MPTE14_LOC_SPAN 24 +#define BM_DIGCTL_MPTE14_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE14_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE14_LOC_SPAN) +#define BP_DIGCTL_MPTE14_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE14_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE14_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE14_LOC_RSVD0) +#define BP_DIGCTL_MPTE14_LOC_LOC 0 +#define BM_DIGCTL_MPTE14_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE14_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE14_LOC_LOC) + +#define HW_DIGCTL_MPTE15_LOC (0x000005f0) + +#define BM_DIGCTL_MPTE15_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE15_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE15_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE15_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE15_LOC_RSVD1) +#define BP_DIGCTL_MPTE15_LOC_SPAN 24 +#define BM_DIGCTL_MPTE15_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE15_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE15_LOC_SPAN) +#define BP_DIGCTL_MPTE15_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE15_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE15_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE15_LOC_RSVD0) +#define BP_DIGCTL_MPTE15_LOC_LOC 0 +#define BM_DIGCTL_MPTE15_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE15_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE15_LOC_LOC) +#endif /* __ARCH_ARM___DIGCTL_H */ diff --git a/arch/arm/mach-mx28/regs-dram.h b/arch/arm/mach-mx28/regs-dram.h new file mode 100644 index 000000000000..ed962a6d5324 --- /dev/null +++ b/arch/arm/mach-mx28/regs-dram.h @@ -0,0 +1,2505 @@ +/* + * Freescale DRAM Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___DRAM_H +#define __ARCH_ARM___DRAM_H + + +#define HW_DRAM_CTL00 (0x00000000) + +#define BP_DRAM_CTL00_USER_DEF_REG_0_1 3 +#define BM_DRAM_CTL00_USER_DEF_REG_0_1 0xFFFFFFF8 +#define BF_DRAM_CTL00_USER_DEF_REG_0_1(v) \ + (((v) << 3) & BM_DRAM_CTL00_USER_DEF_REG_0_1) +#define BM_DRAM_CTL00_CKE_SELECT 0x00000004 +#define BV_DRAM_CTL00_CKE_SELECT__DDR2 0x0 +#define BV_DRAM_CTL00_CKE_SELECT__LPDDR 0x1 +#define BM_DRAM_CTL00_SREFRESH_ENTER 0x00000002 +#define BM_DRAM_CTL00_BRESP_TIMING 0x00000001 +#define BV_DRAM_CTL00_BRESP_TIMING__BUFFERABLE 0x0 +#define BV_DRAM_CTL00_BRESP_TIMING__SEMI_BUFFERABLE 0x1 + +#define HW_DRAM_CTL01 (0x00000004) + +#define BP_DRAM_CTL01_USER_DEF_REG_1 9 +#define BM_DRAM_CTL01_USER_DEF_REG_1 0xFFFFFE00 +#define BF_DRAM_CTL01_USER_DEF_REG_1(v) \ + (((v) << 9) & BM_DRAM_CTL01_USER_DEF_REG_1) +#define BM_DRAM_CTL01_MON_DBG_STB 0x00000100 +#define BP_DRAM_CTL01_SLVERR 4 +#define BM_DRAM_CTL01_SLVERR 0x000000F0 +#define BF_DRAM_CTL01_SLVERR(v) \ + (((v) << 4) & BM_DRAM_CTL01_SLVERR) +#define BP_DRAM_CTL01_MON_DISABLE 0 +#define BM_DRAM_CTL01_MON_DISABLE 0x0000000F +#define BF_DRAM_CTL01_MON_DISABLE(v) \ + (((v) << 0) & BM_DRAM_CTL01_MON_DISABLE) + +#define HW_DRAM_CTL02 (0x00000008) + +#define BP_DRAM_CTL02_USER_DEF_REG_2 0 +#define BM_DRAM_CTL02_USER_DEF_REG_2 0xFFFFFFFF +#define BF_DRAM_CTL02_USER_DEF_REG_2(v) (v) + +#define HW_DRAM_CTL03 (0x0000000c) + +#define BP_DRAM_CTL03_USER_DEF_REG_3 0 +#define BM_DRAM_CTL03_USER_DEF_REG_3 0xFFFFFFFF +#define BF_DRAM_CTL03_USER_DEF_REG_3(v) (v) + +#define HW_DRAM_CTL04 (0x00000010) + +#define BP_DRAM_CTL04_USER_DEF_REG_4 0 +#define BM_DRAM_CTL04_USER_DEF_REG_4 0xFFFFFFFF +#define BF_DRAM_CTL04_USER_DEF_REG_4(v) (v) + +#define HW_DRAM_CTL05 (0x00000014) + +#define BP_DRAM_CTL05_USER_DEF_REG_5 0 +#define BM_DRAM_CTL05_USER_DEF_REG_5 0xFFFFFFFF +#define BF_DRAM_CTL05_USER_DEF_REG_5(v) (v) + +#define HW_DRAM_CTL06 (0x00000018) + +#define BP_DRAM_CTL06_USER_DEF_REG_6 0 +#define BM_DRAM_CTL06_USER_DEF_REG_6 0xFFFFFFFF +#define BF_DRAM_CTL06_USER_DEF_REG_6(v) (v) + +#define HW_DRAM_CTL07 (0x0000001c) + +#define BP_DRAM_CTL07_USER_DEF_REG_7 0 +#define BM_DRAM_CTL07_USER_DEF_REG_7 0xFFFFFFFF +#define BF_DRAM_CTL07_USER_DEF_REG_7(v) (v) + +#define HW_DRAM_CTL08 (0x00000020) + +#define BP_DRAM_CTL08_USER_DEF_REG_RO_0 9 +#define BM_DRAM_CTL08_USER_DEF_REG_RO_0 0xFFFFFE00 +#define BF_DRAM_CTL08_USER_DEF_REG_RO_0(v) \ + (((v) << 9) & BM_DRAM_CTL08_USER_DEF_REG_RO_0) +#define BM_DRAM_CTL08_CONTROLLER_BUSY 0x00000100 +#define BM_DRAM_CTL08_REFRESH_IN_PROCESS 0x00000080 +#define BM_DRAM_CTL08_Q_ALMOST_FULL 0x00000040 +#define BM_DRAM_CTL08_SREFRESH_ACK 0x00000020 +#define BM_DRAM_CTL08_CKE_STATUS 0x00000010 +#define BP_DRAM_CTL08_COMMAND_ACCEPTED 0 +#define BM_DRAM_CTL08_COMMAND_ACCEPTED 0x0000000F +#define BF_DRAM_CTL08_COMMAND_ACCEPTED(v) \ + (((v) << 0) & BM_DRAM_CTL08_COMMAND_ACCEPTED) + +#define HW_DRAM_CTL09 (0x00000024) + +#define BP_DRAM_CTL09_USER_DEF_REG_RO_1 0 +#define BM_DRAM_CTL09_USER_DEF_REG_RO_1 0xFFFFFFFF +#define BF_DRAM_CTL09_USER_DEF_REG_RO_1(v) (v) + +#define HW_DRAM_CTL10 (0x00000028) + +#define BP_DRAM_CTL10_RSVD 24 +#define BM_DRAM_CTL10_RSVD 0xFF000000 +#define BF_DRAM_CTL10_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL10_RSVD) +#define BP_DRAM_CTL10_READ_CNT 16 +#define BM_DRAM_CTL10_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL10_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL10_READ_CNT) +#define BP_DRAM_CTL10_WRESP_CNT 8 +#define BM_DRAM_CTL10_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL10_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL10_WRESP_CNT) +#define BP_DRAM_CTL10_WDATA_CNT 0 +#define BM_DRAM_CTL10_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL10_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL10_WDATA_CNT) + +#define HW_DRAM_CTL11 (0x0000002c) + +#define BP_DRAM_CTL11_WSTATE 24 +#define BM_DRAM_CTL11_WSTATE 0xFF000000 +#define BF_DRAM_CTL11_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL11_WSTATE) +#define BP_DRAM_CTL11_RSTATE 16 +#define BM_DRAM_CTL11_RSTATE 0x00FF0000 +#define BF_DRAM_CTL11_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL11_RSTATE) +#define BP_DRAM_CTL11_RLEN 8 +#define BM_DRAM_CTL11_RLEN 0x0000FF00 +#define BF_DRAM_CTL11_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL11_RLEN) +#define BP_DRAM_CTL11_WLEN 0 +#define BM_DRAM_CTL11_WLEN 0x000000FF +#define BF_DRAM_CTL11_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL11_WLEN) + +#define HW_DRAM_CTL12 (0x00000030) + +#define BP_DRAM_CTL12_RSVD 24 +#define BM_DRAM_CTL12_RSVD 0xFF000000 +#define BF_DRAM_CTL12_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL12_RSVD) +#define BP_DRAM_CTL12_READ_CNT 16 +#define BM_DRAM_CTL12_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL12_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL12_READ_CNT) +#define BP_DRAM_CTL12_WRESP_CNT 8 +#define BM_DRAM_CTL12_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL12_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL12_WRESP_CNT) +#define BP_DRAM_CTL12_WDATA_CNT 0 +#define BM_DRAM_CTL12_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL12_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL12_WDATA_CNT) + +#define HW_DRAM_CTL13 (0x00000034) + +#define BP_DRAM_CTL13_WSTATE 24 +#define BM_DRAM_CTL13_WSTATE 0xFF000000 +#define BF_DRAM_CTL13_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL13_WSTATE) +#define BP_DRAM_CTL13_RSTATE 16 +#define BM_DRAM_CTL13_RSTATE 0x00FF0000 +#define BF_DRAM_CTL13_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL13_RSTATE) +#define BP_DRAM_CTL13_RLEN 8 +#define BM_DRAM_CTL13_RLEN 0x0000FF00 +#define BF_DRAM_CTL13_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL13_RLEN) +#define BP_DRAM_CTL13_WLEN 0 +#define BM_DRAM_CTL13_WLEN 0x000000FF +#define BF_DRAM_CTL13_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL13_WLEN) + +#define HW_DRAM_CTL14 (0x00000038) + +#define BP_DRAM_CTL14_RSVD 24 +#define BM_DRAM_CTL14_RSVD 0xFF000000 +#define BF_DRAM_CTL14_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL14_RSVD) +#define BP_DRAM_CTL14_READ_CNT 16 +#define BM_DRAM_CTL14_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL14_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL14_READ_CNT) +#define BP_DRAM_CTL14_WRESP_CNT 8 +#define BM_DRAM_CTL14_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL14_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL14_WRESP_CNT) +#define BP_DRAM_CTL14_WDATA_CNT 0 +#define BM_DRAM_CTL14_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL14_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL14_WDATA_CNT) + +#define HW_DRAM_CTL15 (0x0000003c) + +#define BP_DRAM_CTL15_WSTATE 24 +#define BM_DRAM_CTL15_WSTATE 0xFF000000 +#define BF_DRAM_CTL15_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL15_WSTATE) +#define BP_DRAM_CTL15_RSTATE 16 +#define BM_DRAM_CTL15_RSTATE 0x00FF0000 +#define BF_DRAM_CTL15_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL15_RSTATE) +#define BP_DRAM_CTL15_RLEN 8 +#define BM_DRAM_CTL15_RLEN 0x0000FF00 +#define BF_DRAM_CTL15_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL15_RLEN) +#define BP_DRAM_CTL15_WLEN 0 +#define BM_DRAM_CTL15_WLEN 0x000000FF +#define BF_DRAM_CTL15_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL15_WLEN) + +#define HW_DRAM_CTL16 (0x00000040) + +#define BP_DRAM_CTL16_RSVD3 25 +#define BM_DRAM_CTL16_RSVD3 0xFE000000 +#define BF_DRAM_CTL16_RSVD3(v) \ + (((v) << 25) & BM_DRAM_CTL16_RSVD3) +#define BM_DRAM_CTL16_WRITE_MODEREG 0x01000000 +#define BP_DRAM_CTL16_RSVD2 17 +#define BM_DRAM_CTL16_RSVD2 0x00FE0000 +#define BF_DRAM_CTL16_RSVD2(v) \ + (((v) << 17) & BM_DRAM_CTL16_RSVD2) +#define BM_DRAM_CTL16_POWER_DOWN 0x00010000 +#define BP_DRAM_CTL16_OBSOLETE 8 +#define BM_DRAM_CTL16_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL16_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL16_OBSOLETE) +#define BP_DRAM_CTL16_RSVD1 1 +#define BM_DRAM_CTL16_RSVD1 0x000000FE +#define BF_DRAM_CTL16_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL16_RSVD1) +#define BM_DRAM_CTL16_START 0x00000001 + +#define HW_DRAM_CTL17 (0x00000044) + +#define BP_DRAM_CTL17_RSVD4 25 +#define BM_DRAM_CTL17_RSVD4 0xFE000000 +#define BF_DRAM_CTL17_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL17_RSVD4) +#define BM_DRAM_CTL17_AUTO_REFRESH_MODE 0x01000000 +#define BP_DRAM_CTL17_RSVD3 17 +#define BM_DRAM_CTL17_RSVD3 0x00FE0000 +#define BF_DRAM_CTL17_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL17_RSVD3) +#define BM_DRAM_CTL17_AREFRESH 0x00010000 +#define BP_DRAM_CTL17_RSVD2 9 +#define BM_DRAM_CTL17_RSVD2 0x0000FE00 +#define BF_DRAM_CTL17_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL17_RSVD2) +#define BM_DRAM_CTL17_ENABLE_QUICK_SREFRESH 0x00000100 +#define BP_DRAM_CTL17_RSVD1 1 +#define BM_DRAM_CTL17_RSVD1 0x000000FE +#define BF_DRAM_CTL17_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL17_RSVD1) +#define BM_DRAM_CTL17_SREFRESH 0x00000001 + +#define HW_DRAM_CTL21 (0x00000054) + +#define BP_DRAM_CTL21_RSVD3 27 +#define BM_DRAM_CTL21_RSVD3 0xF8000000 +#define BF_DRAM_CTL21_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL21_RSVD3) +#define BP_DRAM_CTL21_CKE_DELAY 24 +#define BM_DRAM_CTL21_CKE_DELAY 0x07000000 +#define BF_DRAM_CTL21_CKE_DELAY(v) \ + (((v) << 24) & BM_DRAM_CTL21_CKE_DELAY) +#define BP_DRAM_CTL21_DLL_LOCK 16 +#define BM_DRAM_CTL21_DLL_LOCK 0x00FF0000 +#define BF_DRAM_CTL21_DLL_LOCK(v) \ + (((v) << 16) & BM_DRAM_CTL21_DLL_LOCK) +#define BP_DRAM_CTL21_RSVD2 9 +#define BM_DRAM_CTL21_RSVD2 0x0000FE00 +#define BF_DRAM_CTL21_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL21_RSVD2) +#define BM_DRAM_CTL21_DLLLOCKREG 0x00000100 +#define BP_DRAM_CTL21_RSVD1 1 +#define BM_DRAM_CTL21_RSVD1 0x000000FE +#define BF_DRAM_CTL21_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL21_RSVD1) +#define BM_DRAM_CTL21_DLL_BYPASS_MODE 0x00000001 + +#define HW_DRAM_CTL22 (0x00000058) + +#define BP_DRAM_CTL22_OBSOLETE 24 +#define BM_DRAM_CTL22_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL22_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL22_OBSOLETE) +#define BP_DRAM_CTL22_RSVD3 20 +#define BM_DRAM_CTL22_RSVD3 0x00F00000 +#define BF_DRAM_CTL22_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL22_RSVD3) +#define BP_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE 16 +#define BM_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE 0x000F0000 +#define BF_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE(v) \ + (((v) << 16) & BM_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE) +#define BP_DRAM_CTL22_RSVD2 13 +#define BM_DRAM_CTL22_RSVD2 0x0000E000 +#define BF_DRAM_CTL22_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL22_RSVD2) +#define BP_DRAM_CTL22_LOWPOWER_CONTROL 8 +#define BM_DRAM_CTL22_LOWPOWER_CONTROL 0x00001F00 +#define BF_DRAM_CTL22_LOWPOWER_CONTROL(v) \ + (((v) << 8) & BM_DRAM_CTL22_LOWPOWER_CONTROL) +#define BP_DRAM_CTL22_RSVD1 5 +#define BM_DRAM_CTL22_RSVD1 0x000000E0 +#define BF_DRAM_CTL22_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL22_RSVD1) +#define BP_DRAM_CTL22_LOWPOWER_AUTO_ENABLE 0 +#define BM_DRAM_CTL22_LOWPOWER_AUTO_ENABLE 0x0000001F +#define BF_DRAM_CTL22_LOWPOWER_AUTO_ENABLE(v) \ + (((v) << 0) & BM_DRAM_CTL22_LOWPOWER_AUTO_ENABLE) + +#define HW_DRAM_CTL23 (0x0000005c) + +#define BP_DRAM_CTL23_LOWPOWER_INTERNAL_CNT 16 +#define BM_DRAM_CTL23_LOWPOWER_INTERNAL_CNT 0xFFFF0000 +#define BF_DRAM_CTL23_LOWPOWER_INTERNAL_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL23_LOWPOWER_INTERNAL_CNT) +#define BP_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT 0 +#define BM_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT 0x0000FFFF +#define BF_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT) + +#define HW_DRAM_CTL24 (0x00000060) + +#define BP_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT 16 +#define BM_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT 0xFFFF0000 +#define BF_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT) +#define BP_DRAM_CTL24_LOWPOWER_REFRESH_HOLD 0 +#define BM_DRAM_CTL24_LOWPOWER_REFRESH_HOLD 0x0000FFFF +#define BF_DRAM_CTL24_LOWPOWER_REFRESH_HOLD(v) \ + (((v) << 0) & BM_DRAM_CTL24_LOWPOWER_REFRESH_HOLD) + +#define HW_DRAM_CTL25 (0x00000064) + +#define BP_DRAM_CTL25_OBSOLETE 16 +#define BM_DRAM_CTL25_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL25_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL25_OBSOLETE) +#define BP_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT 0 +#define BM_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT 0x0000FFFF +#define BF_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT) + +#define HW_DRAM_CTL26 (0x00000068) + +#define BP_DRAM_CTL26_OBSOLETE 24 +#define BM_DRAM_CTL26_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL26_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL26_OBSOLETE) +#define BP_DRAM_CTL26_RSVD3 17 +#define BM_DRAM_CTL26_RSVD3 0x00FE0000 +#define BF_DRAM_CTL26_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL26_RSVD3) +#define BM_DRAM_CTL26_PRIORITY_EN 0x00010000 +#define BP_DRAM_CTL26_RSVD2 9 +#define BM_DRAM_CTL26_RSVD2 0x0000FE00 +#define BF_DRAM_CTL26_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL26_RSVD2) +#define BM_DRAM_CTL26_ADDR_CMP_EN 0x00000100 +#define BP_DRAM_CTL26_RSVD1 1 +#define BM_DRAM_CTL26_RSVD1 0x000000FE +#define BF_DRAM_CTL26_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL26_RSVD1) +#define BM_DRAM_CTL26_PLACEMENT_EN 0x00000001 + +#define HW_DRAM_CTL27 (0x0000006c) + +#define BP_DRAM_CTL27_RSVD4 25 +#define BM_DRAM_CTL27_RSVD4 0xFE000000 +#define BF_DRAM_CTL27_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL27_RSVD4) +#define BM_DRAM_CTL27_SWAP_PORT_RW_SAME_EN 0x01000000 +#define BP_DRAM_CTL27_RSVD3 17 +#define BM_DRAM_CTL27_RSVD3 0x00FE0000 +#define BF_DRAM_CTL27_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL27_RSVD3) +#define BM_DRAM_CTL27_SWAP_EN 0x00010000 +#define BP_DRAM_CTL27_RSVD2 9 +#define BM_DRAM_CTL27_RSVD2 0x0000FE00 +#define BF_DRAM_CTL27_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL27_RSVD2) +#define BM_DRAM_CTL27_BANK_SPLIT_EN 0x00000100 +#define BP_DRAM_CTL27_RSVD1 1 +#define BM_DRAM_CTL27_RSVD1 0x000000FE +#define BF_DRAM_CTL27_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL27_RSVD1) +#define BM_DRAM_CTL27_RW_SAME_EN 0x00000001 + +#define HW_DRAM_CTL28 (0x00000070) + +#define BP_DRAM_CTL28_RSVD4 27 +#define BM_DRAM_CTL28_RSVD4 0xF8000000 +#define BF_DRAM_CTL28_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL28_RSVD4) +#define BP_DRAM_CTL28_Q_FULLNESS 24 +#define BM_DRAM_CTL28_Q_FULLNESS 0x07000000 +#define BF_DRAM_CTL28_Q_FULLNESS(v) \ + (((v) << 24) & BM_DRAM_CTL28_Q_FULLNESS) +#define BP_DRAM_CTL28_RSVD3 20 +#define BM_DRAM_CTL28_RSVD3 0x00F00000 +#define BF_DRAM_CTL28_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL28_RSVD3) +#define BP_DRAM_CTL28_AGE_COUNT 16 +#define BM_DRAM_CTL28_AGE_COUNT 0x000F0000 +#define BF_DRAM_CTL28_AGE_COUNT(v) \ + (((v) << 16) & BM_DRAM_CTL28_AGE_COUNT) +#define BP_DRAM_CTL28_RSVD2 12 +#define BM_DRAM_CTL28_RSVD2 0x0000F000 +#define BF_DRAM_CTL28_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL28_RSVD2) +#define BP_DRAM_CTL28_COMMAND_AGE_COUNT 8 +#define BM_DRAM_CTL28_COMMAND_AGE_COUNT 0x00000F00 +#define BF_DRAM_CTL28_COMMAND_AGE_COUNT(v) \ + (((v) << 8) & BM_DRAM_CTL28_COMMAND_AGE_COUNT) +#define BP_DRAM_CTL28_RSVD1 1 +#define BM_DRAM_CTL28_RSVD1 0x000000FE +#define BF_DRAM_CTL28_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL28_RSVD1) +#define BM_DRAM_CTL28_ACTIVE_AGING 0x00000001 + +#define HW_DRAM_CTL29 (0x00000074) + +#define BP_DRAM_CTL29_RSVD4 28 +#define BM_DRAM_CTL29_RSVD4 0xF0000000 +#define BF_DRAM_CTL29_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL29_RSVD4) +#define BP_DRAM_CTL29_CS_MAP 24 +#define BM_DRAM_CTL29_CS_MAP 0x0F000000 +#define BF_DRAM_CTL29_CS_MAP(v) \ + (((v) << 24) & BM_DRAM_CTL29_CS_MAP) +#define BP_DRAM_CTL29_RSVD3 19 +#define BM_DRAM_CTL29_RSVD3 0x00F80000 +#define BF_DRAM_CTL29_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL29_RSVD3) +#define BP_DRAM_CTL29_COLUMN_SIZE 16 +#define BM_DRAM_CTL29_COLUMN_SIZE 0x00070000 +#define BF_DRAM_CTL29_COLUMN_SIZE(v) \ + (((v) << 16) & BM_DRAM_CTL29_COLUMN_SIZE) +#define BP_DRAM_CTL29_RSVD2 11 +#define BM_DRAM_CTL29_RSVD2 0x0000F800 +#define BF_DRAM_CTL29_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL29_RSVD2) +#define BP_DRAM_CTL29_ADDR_PINS 8 +#define BM_DRAM_CTL29_ADDR_PINS 0x00000700 +#define BF_DRAM_CTL29_ADDR_PINS(v) \ + (((v) << 8) & BM_DRAM_CTL29_ADDR_PINS) +#define BP_DRAM_CTL29_RSVD1 4 +#define BM_DRAM_CTL29_RSVD1 0x000000F0 +#define BF_DRAM_CTL29_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL29_RSVD1) +#define BP_DRAM_CTL29_APREBIT 0 +#define BM_DRAM_CTL29_APREBIT 0x0000000F +#define BF_DRAM_CTL29_APREBIT(v) \ + (((v) << 0) & BM_DRAM_CTL29_APREBIT) + +#define HW_DRAM_CTL30 (0x00000078) + +#define BP_DRAM_CTL30_OBSOLETE 24 +#define BM_DRAM_CTL30_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL30_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL30_OBSOLETE) +#define BP_DRAM_CTL30_RSVD3 19 +#define BM_DRAM_CTL30_RSVD3 0x00F80000 +#define BF_DRAM_CTL30_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL30_RSVD3) +#define BP_DRAM_CTL30_MAX_CS_REG 16 +#define BM_DRAM_CTL30_MAX_CS_REG 0x00070000 +#define BF_DRAM_CTL30_MAX_CS_REG(v) \ + (((v) << 16) & BM_DRAM_CTL30_MAX_CS_REG) +#define BP_DRAM_CTL30_RSVD2 12 +#define BM_DRAM_CTL30_RSVD2 0x0000F000 +#define BF_DRAM_CTL30_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL30_RSVD2) +#define BP_DRAM_CTL30_MAX_ROW_REG 8 +#define BM_DRAM_CTL30_MAX_ROW_REG 0x00000F00 +#define BF_DRAM_CTL30_MAX_ROW_REG(v) \ + (((v) << 8) & BM_DRAM_CTL30_MAX_ROW_REG) +#define BP_DRAM_CTL30_RSVD1 4 +#define BM_DRAM_CTL30_RSVD1 0x000000F0 +#define BF_DRAM_CTL30_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL30_RSVD1) +#define BP_DRAM_CTL30_MAX_COL_REG 0 +#define BM_DRAM_CTL30_MAX_COL_REG 0x0000000F +#define BF_DRAM_CTL30_MAX_COL_REG(v) \ + (((v) << 0) & BM_DRAM_CTL30_MAX_COL_REG) + +#define HW_DRAM_CTL31 (0x0000007c) + +#define BP_DRAM_CTL31_OBSOLETE 24 +#define BM_DRAM_CTL31_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL31_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL31_OBSOLETE) +#define BP_DRAM_CTL31_RSVD3 17 +#define BM_DRAM_CTL31_RSVD3 0x00FE0000 +#define BF_DRAM_CTL31_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL31_RSVD3) +#define BM_DRAM_CTL31_EIGHT_BANK_MODE 0x00010000 +#define BP_DRAM_CTL31_RSVD2 9 +#define BM_DRAM_CTL31_RSVD2 0x0000FE00 +#define BF_DRAM_CTL31_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL31_RSVD2) +#define BM_DRAM_CTL31_DRIVE_DQ_DQS 0x00000100 +#define BP_DRAM_CTL31_RSVD1 1 +#define BM_DRAM_CTL31_RSVD1 0x000000FE +#define BF_DRAM_CTL31_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL31_RSVD1) +#define BM_DRAM_CTL31_DQS_N_EN 0x00000001 + +#define HW_DRAM_CTL32 (0x00000080) + +#define BP_DRAM_CTL32_OBSOLETE 16 +#define BM_DRAM_CTL32_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL32_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL32_OBSOLETE) +#define BP_DRAM_CTL32_RSVD2 9 +#define BM_DRAM_CTL32_RSVD2 0x0000FE00 +#define BF_DRAM_CTL32_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL32_RSVD2) +#define BM_DRAM_CTL32_REDUC 0x00000100 +#define BP_DRAM_CTL32_RSVD1 1 +#define BM_DRAM_CTL32_RSVD1 0x000000FE +#define BF_DRAM_CTL32_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL32_RSVD1) +#define BM_DRAM_CTL32_REG_DIMM_ENABLE 0x00000001 + +#define HW_DRAM_CTL33 (0x00000084) + +#define BP_DRAM_CTL33_OBSOLETE 16 +#define BM_DRAM_CTL33_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL33_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL33_OBSOLETE) +#define BP_DRAM_CTL33_RSVD2 9 +#define BM_DRAM_CTL33_RSVD2 0x0000FE00 +#define BF_DRAM_CTL33_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL33_RSVD2) +#define BM_DRAM_CTL33_CONCURRENTAP 0x00000100 +#define BP_DRAM_CTL33_RSVD1 1 +#define BM_DRAM_CTL33_RSVD1 0x000000FE +#define BF_DRAM_CTL33_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL33_RSVD1) +#define BM_DRAM_CTL33_AP 0x00000001 + +#define HW_DRAM_CTL34 (0x00000088) + +#define BP_DRAM_CTL34_RSVD4 25 +#define BM_DRAM_CTL34_RSVD4 0xFE000000 +#define BF_DRAM_CTL34_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL34_RSVD4) +#define BM_DRAM_CTL34_WRITEINTERP 0x01000000 +#define BP_DRAM_CTL34_RSVD3 17 +#define BM_DRAM_CTL34_RSVD3 0x00FE0000 +#define BF_DRAM_CTL34_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL34_RSVD3) +#define BM_DRAM_CTL34_INTRPTWRITEA 0x00010000 +#define BP_DRAM_CTL34_RSVD2 9 +#define BM_DRAM_CTL34_RSVD2 0x0000FE00 +#define BF_DRAM_CTL34_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL34_RSVD2) +#define BM_DRAM_CTL34_INTRPTREADA 0x00000100 +#define BP_DRAM_CTL34_RSVD1 1 +#define BM_DRAM_CTL34_RSVD1 0x000000FE +#define BF_DRAM_CTL34_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL34_RSVD1) +#define BM_DRAM_CTL34_INTRPTAPBURST 0x00000001 + +#define HW_DRAM_CTL35 (0x0000008c) + +#define BP_DRAM_CTL35_OBSOLETE 24 +#define BM_DRAM_CTL35_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL35_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL35_OBSOLETE) +#define BP_DRAM_CTL35_RSVD3 17 +#define BM_DRAM_CTL35_RSVD3 0x00FE0000 +#define BF_DRAM_CTL35_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL35_RSVD3) +#define BM_DRAM_CTL35_PWRUP_SREFRESH_EXIT 0x00010000 +#define BP_DRAM_CTL35_RSVD2 9 +#define BM_DRAM_CTL35_RSVD2 0x0000FE00 +#define BF_DRAM_CTL35_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL35_RSVD2) +#define BM_DRAM_CTL35_NO_CMD_INIT 0x00000100 +#define BP_DRAM_CTL35_RSVD1 4 +#define BM_DRAM_CTL35_RSVD1 0x000000F0 +#define BF_DRAM_CTL35_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL35_RSVD1) +#define BP_DRAM_CTL35_INITAREF 0 +#define BM_DRAM_CTL35_INITAREF 0x0000000F +#define BF_DRAM_CTL35_INITAREF(v) \ + (((v) << 0) & BM_DRAM_CTL35_INITAREF) + +#define HW_DRAM_CTL36 (0x00000090) + +#define BP_DRAM_CTL36_RSVD3 25 +#define BM_DRAM_CTL36_RSVD3 0xFE000000 +#define BF_DRAM_CTL36_RSVD3(v) \ + (((v) << 25) & BM_DRAM_CTL36_RSVD3) +#define BM_DRAM_CTL36_TREF_ENABLE 0x01000000 +#define BP_DRAM_CTL36_RSVD2 17 +#define BM_DRAM_CTL36_RSVD2 0x00FE0000 +#define BF_DRAM_CTL36_RSVD2(v) \ + (((v) << 17) & BM_DRAM_CTL36_RSVD2) +#define BM_DRAM_CTL36_TRAS_LOCKOUT 0x00010000 +#define BP_DRAM_CTL36_OBSOLETE 8 +#define BM_DRAM_CTL36_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL36_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL36_OBSOLETE) +#define BP_DRAM_CTL36_RSVD1 1 +#define BM_DRAM_CTL36_RSVD1 0x000000FE +#define BF_DRAM_CTL36_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL36_RSVD1) +#define BM_DRAM_CTL36_FAST_WRITE 0x00000001 + +#define HW_DRAM_CTL37 (0x00000094) + +#define BP_DRAM_CTL37_RSVD4 28 +#define BM_DRAM_CTL37_RSVD4 0xF0000000 +#define BF_DRAM_CTL37_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL37_RSVD4) +#define BP_DRAM_CTL37_CASLAT_LIN_GATE 24 +#define BM_DRAM_CTL37_CASLAT_LIN_GATE 0x0F000000 +#define BF_DRAM_CTL37_CASLAT_LIN_GATE(v) \ + (((v) << 24) & BM_DRAM_CTL37_CASLAT_LIN_GATE) +#define BP_DRAM_CTL37_RSVD3 20 +#define BM_DRAM_CTL37_RSVD3 0x00F00000 +#define BF_DRAM_CTL37_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL37_RSVD3) +#define BP_DRAM_CTL37_CASLAT_LIN 16 +#define BM_DRAM_CTL37_CASLAT_LIN 0x000F0000 +#define BF_DRAM_CTL37_CASLAT_LIN(v) \ + (((v) << 16) & BM_DRAM_CTL37_CASLAT_LIN) +#define BP_DRAM_CTL37_RSVD2 11 +#define BM_DRAM_CTL37_RSVD2 0x0000F800 +#define BF_DRAM_CTL37_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL37_RSVD2) +#define BP_DRAM_CTL37_CASLAT 8 +#define BM_DRAM_CTL37_CASLAT 0x00000700 +#define BF_DRAM_CTL37_CASLAT(v) \ + (((v) << 8) & BM_DRAM_CTL37_CASLAT) +#define BP_DRAM_CTL37_RSVD1 4 +#define BM_DRAM_CTL37_RSVD1 0x000000F0 +#define BF_DRAM_CTL37_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL37_RSVD1) +#define BP_DRAM_CTL37_WRLAT 0 +#define BM_DRAM_CTL37_WRLAT 0x0000000F +#define BF_DRAM_CTL37_WRLAT(v) \ + (((v) << 0) & BM_DRAM_CTL37_WRLAT) + +#define HW_DRAM_CTL38 (0x00000098) + +#define BP_DRAM_CTL38_RSVD2 29 +#define BM_DRAM_CTL38_RSVD2 0xE0000000 +#define BF_DRAM_CTL38_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL38_RSVD2) +#define BP_DRAM_CTL38_TDAL 24 +#define BM_DRAM_CTL38_TDAL 0x1F000000 +#define BF_DRAM_CTL38_TDAL(v) \ + (((v) << 24) & BM_DRAM_CTL38_TDAL) +#define BP_DRAM_CTL38_TCPD 8 +#define BM_DRAM_CTL38_TCPD 0x00FFFF00 +#define BF_DRAM_CTL38_TCPD(v) \ + (((v) << 8) & BM_DRAM_CTL38_TCPD) +#define BP_DRAM_CTL38_RSVD1 3 +#define BM_DRAM_CTL38_RSVD1 0x000000F8 +#define BF_DRAM_CTL38_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL38_RSVD1) +#define BP_DRAM_CTL38_TCKE 0 +#define BM_DRAM_CTL38_TCKE 0x00000007 +#define BF_DRAM_CTL38_TCKE(v) \ + (((v) << 0) & BM_DRAM_CTL38_TCKE) + +#define HW_DRAM_CTL39 (0x0000009c) + +#define BP_DRAM_CTL39_RSVD1 30 +#define BM_DRAM_CTL39_RSVD1 0xC0000000 +#define BF_DRAM_CTL39_RSVD1(v) \ + (((v) << 30) & BM_DRAM_CTL39_RSVD1) +#define BP_DRAM_CTL39_TFAW 24 +#define BM_DRAM_CTL39_TFAW 0x3F000000 +#define BF_DRAM_CTL39_TFAW(v) \ + (((v) << 24) & BM_DRAM_CTL39_TFAW) +#define BP_DRAM_CTL39_OBSOLETE 16 +#define BM_DRAM_CTL39_OBSOLETE 0x00FF0000 +#define BF_DRAM_CTL39_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL39_OBSOLETE) +#define BP_DRAM_CTL39_TDLL 0 +#define BM_DRAM_CTL39_TDLL 0x0000FFFF +#define BF_DRAM_CTL39_TDLL(v) \ + (((v) << 0) & BM_DRAM_CTL39_TDLL) + +#define HW_DRAM_CTL40 (0x000000a0) + +#define BP_DRAM_CTL40_RSVD1 29 +#define BM_DRAM_CTL40_RSVD1 0xE0000000 +#define BF_DRAM_CTL40_RSVD1(v) \ + (((v) << 29) & BM_DRAM_CTL40_RSVD1) +#define BP_DRAM_CTL40_TMRD 24 +#define BM_DRAM_CTL40_TMRD 0x1F000000 +#define BF_DRAM_CTL40_TMRD(v) \ + (((v) << 24) & BM_DRAM_CTL40_TMRD) +#define BP_DRAM_CTL40_TINIT 0 +#define BM_DRAM_CTL40_TINIT 0x00FFFFFF +#define BF_DRAM_CTL40_TINIT(v) \ + (((v) << 0) & BM_DRAM_CTL40_TINIT) + +#define HW_DRAM_CTL41 (0x000000a4) + +#define BP_DRAM_CTL41_TPDEX 16 +#define BM_DRAM_CTL41_TPDEX 0xFFFF0000 +#define BF_DRAM_CTL41_TPDEX(v) \ + (((v) << 16) & BM_DRAM_CTL41_TPDEX) +#define BP_DRAM_CTL41_TRCD_INT 8 +#define BM_DRAM_CTL41_TRCD_INT 0x0000FF00 +#define BF_DRAM_CTL41_TRCD_INT(v) \ + (((v) << 8) & BM_DRAM_CTL41_TRCD_INT) +#define BP_DRAM_CTL41_RSVD1 6 +#define BM_DRAM_CTL41_RSVD1 0x000000C0 +#define BF_DRAM_CTL41_RSVD1(v) \ + (((v) << 6) & BM_DRAM_CTL41_RSVD1) +#define BP_DRAM_CTL41_TRC 0 +#define BM_DRAM_CTL41_TRC 0x0000003F +#define BF_DRAM_CTL41_TRC(v) \ + (((v) << 0) & BM_DRAM_CTL41_TRC) + +#define HW_DRAM_CTL42 (0x000000a8) + +#define BP_DRAM_CTL42_OBSOLETE 24 +#define BM_DRAM_CTL42_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL42_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL42_OBSOLETE) +#define BP_DRAM_CTL42_TRAS_MAX 8 +#define BM_DRAM_CTL42_TRAS_MAX 0x00FFFF00 +#define BF_DRAM_CTL42_TRAS_MAX(v) \ + (((v) << 8) & BM_DRAM_CTL42_TRAS_MAX) +#define BP_DRAM_CTL42_TRAS_MIN 0 +#define BM_DRAM_CTL42_TRAS_MIN 0x000000FF +#define BF_DRAM_CTL42_TRAS_MIN(v) \ + (((v) << 0) & BM_DRAM_CTL42_TRAS_MIN) + +#define HW_DRAM_CTL43 (0x000000ac) + +#define BP_DRAM_CTL43_RSVD2 28 +#define BM_DRAM_CTL43_RSVD2 0xF0000000 +#define BF_DRAM_CTL43_RSVD2(v) \ + (((v) << 28) & BM_DRAM_CTL43_RSVD2) +#define BP_DRAM_CTL43_TRP 24 +#define BM_DRAM_CTL43_TRP 0x0F000000 +#define BF_DRAM_CTL43_TRP(v) \ + (((v) << 24) & BM_DRAM_CTL43_TRP) +#define BP_DRAM_CTL43_TRFC 16 +#define BM_DRAM_CTL43_TRFC 0x00FF0000 +#define BF_DRAM_CTL43_TRFC(v) \ + (((v) << 16) & BM_DRAM_CTL43_TRFC) +#define BP_DRAM_CTL43_RSVD1 14 +#define BM_DRAM_CTL43_RSVD1 0x0000C000 +#define BF_DRAM_CTL43_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL43_RSVD1) +#define BP_DRAM_CTL43_TREF 0 +#define BM_DRAM_CTL43_TREF 0x00003FFF +#define BF_DRAM_CTL43_TREF(v) \ + (((v) << 0) & BM_DRAM_CTL43_TREF) + +#define HW_DRAM_CTL44 (0x000000b0) + +#define BP_DRAM_CTL44_RSVD4 28 +#define BM_DRAM_CTL44_RSVD4 0xF0000000 +#define BF_DRAM_CTL44_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL44_RSVD4) +#define BP_DRAM_CTL44_TWTR 24 +#define BM_DRAM_CTL44_TWTR 0x0F000000 +#define BF_DRAM_CTL44_TWTR(v) \ + (((v) << 24) & BM_DRAM_CTL44_TWTR) +#define BP_DRAM_CTL44_RSVD3 21 +#define BM_DRAM_CTL44_RSVD3 0x00E00000 +#define BF_DRAM_CTL44_RSVD3(v) \ + (((v) << 21) & BM_DRAM_CTL44_RSVD3) +#define BP_DRAM_CTL44_TWR_INT 16 +#define BM_DRAM_CTL44_TWR_INT 0x001F0000 +#define BF_DRAM_CTL44_TWR_INT(v) \ + (((v) << 16) & BM_DRAM_CTL44_TWR_INT) +#define BP_DRAM_CTL44_RSVD2 11 +#define BM_DRAM_CTL44_RSVD2 0x0000F800 +#define BF_DRAM_CTL44_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL44_RSVD2) +#define BP_DRAM_CTL44_TRTP 8 +#define BM_DRAM_CTL44_TRTP 0x00000700 +#define BF_DRAM_CTL44_TRTP(v) \ + (((v) << 8) & BM_DRAM_CTL44_TRTP) +#define BP_DRAM_CTL44_RSVD1 3 +#define BM_DRAM_CTL44_RSVD1 0x000000F8 +#define BF_DRAM_CTL44_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL44_RSVD1) +#define BP_DRAM_CTL44_TRRD 0 +#define BM_DRAM_CTL44_TRRD 0x00000007 +#define BF_DRAM_CTL44_TRRD(v) \ + (((v) << 0) & BM_DRAM_CTL44_TRRD) + +#define HW_DRAM_CTL45 (0x000000b4) + +#define BP_DRAM_CTL45_TXSR 16 +#define BM_DRAM_CTL45_TXSR 0xFFFF0000 +#define BF_DRAM_CTL45_TXSR(v) \ + (((v) << 16) & BM_DRAM_CTL45_TXSR) +#define BP_DRAM_CTL45_TXSNR 0 +#define BM_DRAM_CTL45_TXSNR 0x0000FFFF +#define BF_DRAM_CTL45_TXSNR(v) \ + (((v) << 0) & BM_DRAM_CTL45_TXSNR) + +#define HW_DRAM_CTL48 (0x000000c0) + +#define BM_DRAM_CTL48_RSVD4 0x80000000 +#define BP_DRAM_CTL48_AXI0_CURRENT_BDW 24 +#define BM_DRAM_CTL48_AXI0_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL48_AXI0_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL48_AXI0_CURRENT_BDW) +#define BP_DRAM_CTL48_RSVD3 17 +#define BM_DRAM_CTL48_RSVD3 0x00FE0000 +#define BF_DRAM_CTL48_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL48_RSVD3) +#define BM_DRAM_CTL48_AXI0_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL48_RSVD2 0x00008000 +#define BP_DRAM_CTL48_AXI0_BDW 8 +#define BM_DRAM_CTL48_AXI0_BDW 0x00007F00 +#define BF_DRAM_CTL48_AXI0_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL48_AXI0_BDW) +#define BP_DRAM_CTL48_RSVD1 2 +#define BM_DRAM_CTL48_RSVD1 0x000000FC +#define BF_DRAM_CTL48_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL48_RSVD1) +#define BP_DRAM_CTL48_AXI0_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL48_AXI0_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL48_AXI0_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL48_AXI0_FIFO_TYPE_REG) + +#define HW_DRAM_CTL49 (0x000000c4) + +#define BP_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL49_RSVD2 11 +#define BM_DRAM_CTL49_RSVD2 0x0000F800 +#define BF_DRAM_CTL49_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL49_RSVD2) +#define BP_DRAM_CTL49_AXI0_W_PRIORITY 8 +#define BM_DRAM_CTL49_AXI0_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL49_AXI0_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL49_AXI0_W_PRIORITY) +#define BP_DRAM_CTL49_RSVD1 3 +#define BM_DRAM_CTL49_RSVD1 0x000000F8 +#define BF_DRAM_CTL49_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL49_RSVD1) +#define BP_DRAM_CTL49_AXI0_R_PRIORITY 0 +#define BM_DRAM_CTL49_AXI0_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL49_AXI0_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL49_AXI0_R_PRIORITY) + +#define HW_DRAM_CTL50 (0x000000c8) + +#define BM_DRAM_CTL50_RSVD4 0x80000000 +#define BP_DRAM_CTL50_AXI1_CURRENT_BDW 24 +#define BM_DRAM_CTL50_AXI1_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL50_AXI1_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL50_AXI1_CURRENT_BDW) +#define BP_DRAM_CTL50_RSVD3 17 +#define BM_DRAM_CTL50_RSVD3 0x00FE0000 +#define BF_DRAM_CTL50_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL50_RSVD3) +#define BM_DRAM_CTL50_AXI1_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL50_RSVD2 0x00008000 +#define BP_DRAM_CTL50_AXI1_BDW 8 +#define BM_DRAM_CTL50_AXI1_BDW 0x00007F00 +#define BF_DRAM_CTL50_AXI1_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL50_AXI1_BDW) +#define BP_DRAM_CTL50_RSVD1 2 +#define BM_DRAM_CTL50_RSVD1 0x000000FC +#define BF_DRAM_CTL50_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL50_RSVD1) +#define BP_DRAM_CTL50_AXI1_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL50_AXI1_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL50_AXI1_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL50_AXI1_FIFO_TYPE_REG) + +#define HW_DRAM_CTL51 (0x000000cc) + +#define BP_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL51_RSVD2 11 +#define BM_DRAM_CTL51_RSVD2 0x0000F800 +#define BF_DRAM_CTL51_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL51_RSVD2) +#define BP_DRAM_CTL51_AXI1_W_PRIORITY 8 +#define BM_DRAM_CTL51_AXI1_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL51_AXI1_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL51_AXI1_W_PRIORITY) +#define BP_DRAM_CTL51_RSVD1 3 +#define BM_DRAM_CTL51_RSVD1 0x000000F8 +#define BF_DRAM_CTL51_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL51_RSVD1) +#define BP_DRAM_CTL51_AXI1_R_PRIORITY 0 +#define BM_DRAM_CTL51_AXI1_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL51_AXI1_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL51_AXI1_R_PRIORITY) + +#define HW_DRAM_CTL52 (0x000000d0) + +#define BM_DRAM_CTL52_RSVD4 0x80000000 +#define BP_DRAM_CTL52_AXI2_CURRENT_BDW 24 +#define BM_DRAM_CTL52_AXI2_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL52_AXI2_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL52_AXI2_CURRENT_BDW) +#define BP_DRAM_CTL52_RSVD3 17 +#define BM_DRAM_CTL52_RSVD3 0x00FE0000 +#define BF_DRAM_CTL52_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL52_RSVD3) +#define BM_DRAM_CTL52_AXI2_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL52_RSVD2 0x00008000 +#define BP_DRAM_CTL52_AXI2_BDW 8 +#define BM_DRAM_CTL52_AXI2_BDW 0x00007F00 +#define BF_DRAM_CTL52_AXI2_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL52_AXI2_BDW) +#define BP_DRAM_CTL52_RSVD1 2 +#define BM_DRAM_CTL52_RSVD1 0x000000FC +#define BF_DRAM_CTL52_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL52_RSVD1) +#define BP_DRAM_CTL52_AXI2_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL52_AXI2_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL52_AXI2_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL52_AXI2_FIFO_TYPE_REG) + +#define HW_DRAM_CTL53 (0x000000d4) + +#define BP_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL53_RSVD2 11 +#define BM_DRAM_CTL53_RSVD2 0x0000F800 +#define BF_DRAM_CTL53_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL53_RSVD2) +#define BP_DRAM_CTL53_AXI2_W_PRIORITY 8 +#define BM_DRAM_CTL53_AXI2_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL53_AXI2_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL53_AXI2_W_PRIORITY) +#define BP_DRAM_CTL53_RSVD1 3 +#define BM_DRAM_CTL53_RSVD1 0x000000F8 +#define BF_DRAM_CTL53_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL53_RSVD1) +#define BP_DRAM_CTL53_AXI2_R_PRIORITY 0 +#define BM_DRAM_CTL53_AXI2_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL53_AXI2_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL53_AXI2_R_PRIORITY) + +#define HW_DRAM_CTL54 (0x000000d8) + +#define BM_DRAM_CTL54_RSVD4 0x80000000 +#define BP_DRAM_CTL54_AXI3_CURRENT_BDW 24 +#define BM_DRAM_CTL54_AXI3_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL54_AXI3_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL54_AXI3_CURRENT_BDW) +#define BP_DRAM_CTL54_RSVD3 17 +#define BM_DRAM_CTL54_RSVD3 0x00FE0000 +#define BF_DRAM_CTL54_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL54_RSVD3) +#define BM_DRAM_CTL54_AXI3_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL54_RSVD2 0x00008000 +#define BP_DRAM_CTL54_AXI3_BDW 8 +#define BM_DRAM_CTL54_AXI3_BDW 0x00007F00 +#define BF_DRAM_CTL54_AXI3_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL54_AXI3_BDW) +#define BP_DRAM_CTL54_RSVD1 2 +#define BM_DRAM_CTL54_RSVD1 0x000000FC +#define BF_DRAM_CTL54_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL54_RSVD1) +#define BP_DRAM_CTL54_AXI3_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL54_AXI3_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL54_AXI3_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL54_AXI3_FIFO_TYPE_REG) + +#define HW_DRAM_CTL55 (0x000000dc) + +#define BP_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL55_RSVD2 11 +#define BM_DRAM_CTL55_RSVD2 0x0000F800 +#define BF_DRAM_CTL55_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL55_RSVD2) +#define BP_DRAM_CTL55_AXI3_W_PRIORITY 8 +#define BM_DRAM_CTL55_AXI3_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL55_AXI3_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL55_AXI3_W_PRIORITY) +#define BP_DRAM_CTL55_RSVD1 3 +#define BM_DRAM_CTL55_RSVD1 0x000000F8 +#define BF_DRAM_CTL55_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL55_RSVD1) +#define BP_DRAM_CTL55_AXI3_R_PRIORITY 0 +#define BM_DRAM_CTL55_AXI3_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL55_AXI3_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL55_AXI3_R_PRIORITY) + +#define HW_DRAM_CTL56 (0x000000e0) + +#define BP_DRAM_CTL56_OBSOLETE 8 +#define BM_DRAM_CTL56_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL56_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL56_OBSOLETE) +#define BP_DRAM_CTL56_RSVD1 3 +#define BM_DRAM_CTL56_RSVD1 0x000000F8 +#define BF_DRAM_CTL56_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL56_RSVD1) +#define BP_DRAM_CTL56_ARB_CMD_Q_THRESHOLD 0 +#define BM_DRAM_CTL56_ARB_CMD_Q_THRESHOLD 0x00000007 +#define BF_DRAM_CTL56_ARB_CMD_Q_THRESHOLD(v) \ + (((v) << 0) & BM_DRAM_CTL56_ARB_CMD_Q_THRESHOLD) + +#define HW_DRAM_CTL58 (0x000000e8) + +#define BP_DRAM_CTL58_RSVD2 27 +#define BM_DRAM_CTL58_RSVD2 0xF8000000 +#define BF_DRAM_CTL58_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL58_RSVD2) +#define BP_DRAM_CTL58_INT_STATUS 16 +#define BM_DRAM_CTL58_INT_STATUS 0x07FF0000 +#define BF_DRAM_CTL58_INT_STATUS(v) \ + (((v) << 16) & BM_DRAM_CTL58_INT_STATUS) +#define BP_DRAM_CTL58_RSVD1 11 +#define BM_DRAM_CTL58_RSVD1 0x0000F800 +#define BF_DRAM_CTL58_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL58_RSVD1) +#define BP_DRAM_CTL58_INT_MASK 0 +#define BM_DRAM_CTL58_INT_MASK 0x000007FF +#define BF_DRAM_CTL58_INT_MASK(v) \ + (((v) << 0) & BM_DRAM_CTL58_INT_MASK) + +#define HW_DRAM_CTL59 (0x000000ec) + +#define BP_DRAM_CTL59_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL59_OUT_OF_RANGE_ADDR 0xFFFFFFFF +#define BF_DRAM_CTL59_OUT_OF_RANGE_ADDR(v) (v) + +#define HW_DRAM_CTL60 (0x000000f0) + +#define BP_DRAM_CTL60_OBSOLETE 8 +#define BM_DRAM_CTL60_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL60_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL60_OBSOLETE) +#define BP_DRAM_CTL60_RSVD1 2 +#define BM_DRAM_CTL60_RSVD1 0x000000FC +#define BF_DRAM_CTL60_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL60_RSVD1) +#define BP_DRAM_CTL60_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL60_OUT_OF_RANGE_ADDR 0x00000003 +#define BF_DRAM_CTL60_OUT_OF_RANGE_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL60_OUT_OF_RANGE_ADDR) + +#define HW_DRAM_CTL61 (0x000000f4) + +#define BP_DRAM_CTL61_RSVD3 30 +#define BM_DRAM_CTL61_RSVD3 0xC0000000 +#define BF_DRAM_CTL61_RSVD3(v) \ + (((v) << 30) & BM_DRAM_CTL61_RSVD3) +#define BP_DRAM_CTL61_OUT_OF_RANGE_TYPE 24 +#define BM_DRAM_CTL61_OUT_OF_RANGE_TYPE 0x3F000000 +#define BF_DRAM_CTL61_OUT_OF_RANGE_TYPE(v) \ + (((v) << 24) & BM_DRAM_CTL61_OUT_OF_RANGE_TYPE) +#define BM_DRAM_CTL61_RSVD2 0x00800000 +#define BP_DRAM_CTL61_OUT_OF_RANGE_LENGTH 16 +#define BM_DRAM_CTL61_OUT_OF_RANGE_LENGTH 0x007F0000 +#define BF_DRAM_CTL61_OUT_OF_RANGE_LENGTH(v) \ + (((v) << 16) & BM_DRAM_CTL61_OUT_OF_RANGE_LENGTH) +#define BP_DRAM_CTL61_RSVD1 13 +#define BM_DRAM_CTL61_RSVD1 0x0000E000 +#define BF_DRAM_CTL61_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL61_RSVD1) +#define BP_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID 0 +#define BM_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID 0x00001FFF +#define BF_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID(v) \ + (((v) << 0) & BM_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID) + +#define HW_DRAM_CTL62 (0x000000f8) + +#define BP_DRAM_CTL62_PORT_CMD_ERROR_ADDR 0 +#define BM_DRAM_CTL62_PORT_CMD_ERROR_ADDR 0xFFFFFFFF +#define BF_DRAM_CTL62_PORT_CMD_ERROR_ADDR(v) (v) + +#define HW_DRAM_CTL63 (0x000000fc) + +#define BP_DRAM_CTL63_OBSOLETE 8 +#define BM_DRAM_CTL63_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL63_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL63_OBSOLETE) +#define BP_DRAM_CTL63_RSVD1 2 +#define BM_DRAM_CTL63_RSVD1 0x000000FC +#define BF_DRAM_CTL63_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL63_RSVD1) +#define BP_DRAM_CTL63_PORT_CMD_ERROR_ADDR 0 +#define BM_DRAM_CTL63_PORT_CMD_ERROR_ADDR 0x00000003 +#define BF_DRAM_CTL63_PORT_CMD_ERROR_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL63_PORT_CMD_ERROR_ADDR) + +#define HW_DRAM_CTL64 (0x00000100) + +#define BP_DRAM_CTL64_OBSOLETE 24 +#define BM_DRAM_CTL64_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL64_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL64_OBSOLETE) +#define BP_DRAM_CTL64_RSVD2 21 +#define BM_DRAM_CTL64_RSVD2 0x00E00000 +#define BF_DRAM_CTL64_RSVD2(v) \ + (((v) << 21) & BM_DRAM_CTL64_RSVD2) +#define BP_DRAM_CTL64_PORT_CMD_ERROR_ID 8 +#define BM_DRAM_CTL64_PORT_CMD_ERROR_ID 0x001FFF00 +#define BF_DRAM_CTL64_PORT_CMD_ERROR_ID(v) \ + (((v) << 8) & BM_DRAM_CTL64_PORT_CMD_ERROR_ID) +#define BP_DRAM_CTL64_RSVD1 4 +#define BM_DRAM_CTL64_RSVD1 0x000000F0 +#define BF_DRAM_CTL64_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL64_RSVD1) +#define BP_DRAM_CTL64_PORT_CMD_ERROR_TYPE 0 +#define BM_DRAM_CTL64_PORT_CMD_ERROR_TYPE 0x0000000F +#define BF_DRAM_CTL64_PORT_CMD_ERROR_TYPE(v) \ + (((v) << 0) & BM_DRAM_CTL64_PORT_CMD_ERROR_TYPE) + +#define HW_DRAM_CTL65 (0x00000104) + +#define BP_DRAM_CTL65_OBSOLETE 24 +#define BM_DRAM_CTL65_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL65_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL65_OBSOLETE) +#define BP_DRAM_CTL65_RSVD2 21 +#define BM_DRAM_CTL65_RSVD2 0x00E00000 +#define BF_DRAM_CTL65_RSVD2(v) \ + (((v) << 21) & BM_DRAM_CTL65_RSVD2) +#define BP_DRAM_CTL65_PORT_DATA_ERROR_ID 8 +#define BM_DRAM_CTL65_PORT_DATA_ERROR_ID 0x001FFF00 +#define BF_DRAM_CTL65_PORT_DATA_ERROR_ID(v) \ + (((v) << 8) & BM_DRAM_CTL65_PORT_DATA_ERROR_ID) +#define BP_DRAM_CTL65_RSVD1 3 +#define BM_DRAM_CTL65_RSVD1 0x000000F8 +#define BF_DRAM_CTL65_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL65_RSVD1) +#define BP_DRAM_CTL65_PORT_DATA_ERROR_TYPE 0 +#define BM_DRAM_CTL65_PORT_DATA_ERROR_TYPE 0x00000007 +#define BF_DRAM_CTL65_PORT_DATA_ERROR_TYPE(v) \ + (((v) << 0) & BM_DRAM_CTL65_PORT_DATA_ERROR_TYPE) + +#define HW_DRAM_CTL66 (0x00000108) + +#define BP_DRAM_CTL66_OBSOLETE 24 +#define BM_DRAM_CTL66_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL66_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL66_OBSOLETE) +#define BP_DRAM_CTL66_RSVD2 20 +#define BM_DRAM_CTL66_RSVD2 0x00F00000 +#define BF_DRAM_CTL66_RSVD2(v) \ + (((v) << 20) & BM_DRAM_CTL66_RSVD2) +#define BP_DRAM_CTL66_TDFI_CTRLUPD_MIN 16 +#define BM_DRAM_CTL66_TDFI_CTRLUPD_MIN 0x000F0000 +#define BF_DRAM_CTL66_TDFI_CTRLUPD_MIN(v) \ + (((v) << 16) & BM_DRAM_CTL66_TDFI_CTRLUPD_MIN) +#define BP_DRAM_CTL66_RSVD1 14 +#define BM_DRAM_CTL66_RSVD1 0x0000C000 +#define BF_DRAM_CTL66_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL66_RSVD1) +#define BP_DRAM_CTL66_TDFI_CTRLUPD_MAX 0 +#define BM_DRAM_CTL66_TDFI_CTRLUPD_MAX 0x00003FFF +#define BF_DRAM_CTL66_TDFI_CTRLUPD_MAX(v) \ + (((v) << 0) & BM_DRAM_CTL66_TDFI_CTRLUPD_MAX) + +#define HW_DRAM_CTL67 (0x0000010c) + +#define BP_DRAM_CTL67_RSVD4 28 +#define BM_DRAM_CTL67_RSVD4 0xF0000000 +#define BF_DRAM_CTL67_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL67_RSVD4) +#define BP_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE 24 +#define BM_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE 0x0F000000 +#define BF_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE(v) \ + (((v) << 24) & BM_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE) +#define BP_DRAM_CTL67_RSVD3 19 +#define BM_DRAM_CTL67_RSVD3 0x00F80000 +#define BF_DRAM_CTL67_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL67_RSVD3) +#define BP_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE 16 +#define BM_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE 0x00070000 +#define BF_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE(v) \ + (((v) << 16) & BM_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE) +#define BP_DRAM_CTL67_RSVD2 12 +#define BM_DRAM_CTL67_RSVD2 0x0000F000 +#define BF_DRAM_CTL67_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL67_RSVD2) +#define BP_DRAM_CTL67_DRAM_CLK_ENABLE 8 +#define BM_DRAM_CTL67_DRAM_CLK_ENABLE 0x00000F00 +#define BF_DRAM_CTL67_DRAM_CLK_ENABLE(v) \ + (((v) << 8) & BM_DRAM_CTL67_DRAM_CLK_ENABLE) +#define BP_DRAM_CTL67_RSVD1 4 +#define BM_DRAM_CTL67_RSVD1 0x000000F0 +#define BF_DRAM_CTL67_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL67_RSVD1) +#define BP_DRAM_CTL67_TDFI_CTRL_DELAY 0 +#define BM_DRAM_CTL67_TDFI_CTRL_DELAY 0x0000000F +#define BF_DRAM_CTL67_TDFI_CTRL_DELAY(v) \ + (((v) << 0) & BM_DRAM_CTL67_TDFI_CTRL_DELAY) + +#define HW_DRAM_CTL68 (0x00000110) + +#define BP_DRAM_CTL68_RSVD2 30 +#define BM_DRAM_CTL68_RSVD2 0xC0000000 +#define BF_DRAM_CTL68_RSVD2(v) \ + (((v) << 30) & BM_DRAM_CTL68_RSVD2) +#define BP_DRAM_CTL68_TDFI_PHYUPD_TYPE0 16 +#define BM_DRAM_CTL68_TDFI_PHYUPD_TYPE0 0x3FFF0000 +#define BF_DRAM_CTL68_TDFI_PHYUPD_TYPE0(v) \ + (((v) << 16) & BM_DRAM_CTL68_TDFI_PHYUPD_TYPE0) +#define BP_DRAM_CTL68_RSVD1 14 +#define BM_DRAM_CTL68_RSVD1 0x0000C000 +#define BF_DRAM_CTL68_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL68_RSVD1) +#define BP_DRAM_CTL68_TDFI_PHYUPD_RESP 0 +#define BM_DRAM_CTL68_TDFI_PHYUPD_RESP 0x00003FFF +#define BF_DRAM_CTL68_TDFI_PHYUPD_RESP(v) \ + (((v) << 0) & BM_DRAM_CTL68_TDFI_PHYUPD_RESP) + +#define HW_DRAM_CTL69 (0x00000114) + +#define BP_DRAM_CTL69_OBSOLETE 16 +#define BM_DRAM_CTL69_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL69_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL69_OBSOLETE) +#define BP_DRAM_CTL69_RSVD2 12 +#define BM_DRAM_CTL69_RSVD2 0x0000F000 +#define BF_DRAM_CTL69_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL69_RSVD2) +#define BP_DRAM_CTL69_TDFI_PHY_WRLAT_BASE 8 +#define BM_DRAM_CTL69_TDFI_PHY_WRLAT_BASE 0x00000F00 +#define BF_DRAM_CTL69_TDFI_PHY_WRLAT_BASE(v) \ + (((v) << 8) & BM_DRAM_CTL69_TDFI_PHY_WRLAT_BASE) +#define BP_DRAM_CTL69_RSVD1 4 +#define BM_DRAM_CTL69_RSVD1 0x000000F0 +#define BF_DRAM_CTL69_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL69_RSVD1) +#define BP_DRAM_CTL69_TDFI_PHY_WRLAT 0 +#define BM_DRAM_CTL69_TDFI_PHY_WRLAT 0x0000000F +#define BF_DRAM_CTL69_TDFI_PHY_WRLAT(v) \ + (((v) << 0) & BM_DRAM_CTL69_TDFI_PHY_WRLAT) + +#define HW_DRAM_CTL70 (0x00000118) + +#define BP_DRAM_CTL70_OBSOLETE 24 +#define BM_DRAM_CTL70_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL70_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL70_OBSOLETE) +#define BP_DRAM_CTL70_RSVD3 20 +#define BM_DRAM_CTL70_RSVD3 0x00F00000 +#define BF_DRAM_CTL70_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL70_RSVD3) +#define BP_DRAM_CTL70_TDFI_RDDATA_EN_BASE 16 +#define BM_DRAM_CTL70_TDFI_RDDATA_EN_BASE 0x000F0000 +#define BF_DRAM_CTL70_TDFI_RDDATA_EN_BASE(v) \ + (((v) << 16) & BM_DRAM_CTL70_TDFI_RDDATA_EN_BASE) +#define BP_DRAM_CTL70_RSVD2 12 +#define BM_DRAM_CTL70_RSVD2 0x0000F000 +#define BF_DRAM_CTL70_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL70_RSVD2) +#define BP_DRAM_CTL70_TDFI_RDDATA_EN 8 +#define BM_DRAM_CTL70_TDFI_RDDATA_EN 0x00000F00 +#define BF_DRAM_CTL70_TDFI_RDDATA_EN(v) \ + (((v) << 8) & BM_DRAM_CTL70_TDFI_RDDATA_EN) +#define BP_DRAM_CTL70_RSVD1 4 +#define BM_DRAM_CTL70_RSVD1 0x000000F0 +#define BF_DRAM_CTL70_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL70_RSVD1) +#define BP_DRAM_CTL70_TDFI_PHY_RDLAT 0 +#define BM_DRAM_CTL70_TDFI_PHY_RDLAT 0x0000000F +#define BF_DRAM_CTL70_TDFI_PHY_RDLAT(v) \ + (((v) << 0) & BM_DRAM_CTL70_TDFI_PHY_RDLAT) + +#define HW_DRAM_CTL71 (0x0000011c) + +#define BP_DRAM_CTL71_PHY_CTRL_REG_0_0 0 +#define BM_DRAM_CTL71_PHY_CTRL_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL71_PHY_CTRL_REG_0_0(v) (v) + +#define HW_DRAM_CTL72 (0x00000120) + +#define BP_DRAM_CTL72_PHY_CTRL_REG_0_1 0 +#define BM_DRAM_CTL72_PHY_CTRL_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL72_PHY_CTRL_REG_0_1(v) (v) + +#define HW_DRAM_CTL73 (0x00000124) + +#define BP_DRAM_CTL73_PHY_CTRL_REG_0_2 0 +#define BM_DRAM_CTL73_PHY_CTRL_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL73_PHY_CTRL_REG_0_2(v) (v) + +#define HW_DRAM_CTL74 (0x00000128) + +#define BP_DRAM_CTL74_PHY_CTRL_REG_0_3 0 +#define BM_DRAM_CTL74_PHY_CTRL_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL74_PHY_CTRL_REG_0_3(v) (v) + +#define HW_DRAM_CTL75 (0x0000012c) + +#define BP_DRAM_CTL75_PHY_CTRL_REG_1_0 0 +#define BM_DRAM_CTL75_PHY_CTRL_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL75_PHY_CTRL_REG_1_0(v) (v) + +#define HW_DRAM_CTL76 (0x00000130) + +#define BP_DRAM_CTL76_PHY_CTRL_REG_1_1 0 +#define BM_DRAM_CTL76_PHY_CTRL_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL76_PHY_CTRL_REG_1_1(v) (v) + +#define HW_DRAM_CTL77 (0x00000134) + +#define BP_DRAM_CTL77_PHY_CTRL_REG_1_2 0 +#define BM_DRAM_CTL77_PHY_CTRL_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL77_PHY_CTRL_REG_1_2(v) (v) + +#define HW_DRAM_CTL78 (0x00000138) + +#define BP_DRAM_CTL78_PHY_CTRL_REG_1_3 0 +#define BM_DRAM_CTL78_PHY_CTRL_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL78_PHY_CTRL_REG_1_3(v) (v) + +#define HW_DRAM_CTL79 (0x0000013c) + +#define BP_DRAM_CTL79_PHY_CTRL_REG_2 0 +#define BM_DRAM_CTL79_PHY_CTRL_REG_2 0xFFFFFFFF +#define BF_DRAM_CTL79_PHY_CTRL_REG_2(v) (v) + +#define HW_DRAM_CTL80 (0x00000140) + +#define BP_DRAM_CTL80_DFT_CTRL_REG 0 +#define BM_DRAM_CTL80_DFT_CTRL_REG 0xFFFFFFFF +#define BF_DRAM_CTL80_DFT_CTRL_REG(v) (v) + +#define HW_DRAM_CTL81 (0x00000144) + +#define BP_DRAM_CTL81_OBSOLETE 16 +#define BM_DRAM_CTL81_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL81_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL81_OBSOLETE) +#define BP_DRAM_CTL81_RSVD2 13 +#define BM_DRAM_CTL81_RSVD2 0x0000E000 +#define BF_DRAM_CTL81_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL81_RSVD2) +#define BP_DRAM_CTL81_OCD_ADJUST_PUP_CS_0 8 +#define BM_DRAM_CTL81_OCD_ADJUST_PUP_CS_0 0x00001F00 +#define BF_DRAM_CTL81_OCD_ADJUST_PUP_CS_0(v) \ + (((v) << 8) & BM_DRAM_CTL81_OCD_ADJUST_PUP_CS_0) +#define BP_DRAM_CTL81_RSVD1 5 +#define BM_DRAM_CTL81_RSVD1 0x000000E0 +#define BF_DRAM_CTL81_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL81_RSVD1) +#define BP_DRAM_CTL81_OCD_ADJUST_PDN_CS_0 0 +#define BM_DRAM_CTL81_OCD_ADJUST_PDN_CS_0 0x0000001F +#define BF_DRAM_CTL81_OCD_ADJUST_PDN_CS_0(v) \ + (((v) << 0) & BM_DRAM_CTL81_OCD_ADJUST_PDN_CS_0) + +#define HW_DRAM_CTL82 (0x00000148) + +#define BP_DRAM_CTL82_RSVD1 25 +#define BM_DRAM_CTL82_RSVD1 0xFE000000 +#define BF_DRAM_CTL82_RSVD1(v) \ + (((v) << 25) & BM_DRAM_CTL82_RSVD1) +#define BM_DRAM_CTL82_ODT_ALT_EN 0x01000000 +#define BP_DRAM_CTL82_OBSOLETE 0 +#define BM_DRAM_CTL82_OBSOLETE 0x00FFFFFF +#define BF_DRAM_CTL82_OBSOLETE(v) \ + (((v) << 0) & BM_DRAM_CTL82_OBSOLETE) + +#define HW_DRAM_CTL83 (0x0000014c) + +#define BP_DRAM_CTL83_RSVD4 28 +#define BM_DRAM_CTL83_RSVD4 0xF0000000 +#define BF_DRAM_CTL83_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL83_RSVD4) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS3 24 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS3 0x0F000000 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS3(v) \ + (((v) << 24) & BM_DRAM_CTL83_ODT_RD_MAP_CS3) +#define BP_DRAM_CTL83_RSVD3 20 +#define BM_DRAM_CTL83_RSVD3 0x00F00000 +#define BF_DRAM_CTL83_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL83_RSVD3) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS2 16 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS2 0x000F0000 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS2(v) \ + (((v) << 16) & BM_DRAM_CTL83_ODT_RD_MAP_CS2) +#define BP_DRAM_CTL83_RSVD2 12 +#define BM_DRAM_CTL83_RSVD2 0x0000F000 +#define BF_DRAM_CTL83_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL83_RSVD2) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS1 8 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS1 0x00000F00 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS1(v) \ + (((v) << 8) & BM_DRAM_CTL83_ODT_RD_MAP_CS1) +#define BP_DRAM_CTL83_RSVD1 4 +#define BM_DRAM_CTL83_RSVD1 0x000000F0 +#define BF_DRAM_CTL83_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL83_RSVD1) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS0 0 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS0 0x0000000F +#define BF_DRAM_CTL83_ODT_RD_MAP_CS0(v) \ + (((v) << 0) & BM_DRAM_CTL83_ODT_RD_MAP_CS0) + +#define HW_DRAM_CTL84 (0x00000150) + +#define BP_DRAM_CTL84_RSVD4 28 +#define BM_DRAM_CTL84_RSVD4 0xF0000000 +#define BF_DRAM_CTL84_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL84_RSVD4) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS3 24 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS3 0x0F000000 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS3(v) \ + (((v) << 24) & BM_DRAM_CTL84_ODT_WR_MAP_CS3) +#define BP_DRAM_CTL84_RSVD3 20 +#define BM_DRAM_CTL84_RSVD3 0x00F00000 +#define BF_DRAM_CTL84_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL84_RSVD3) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS2 16 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS2 0x000F0000 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS2(v) \ + (((v) << 16) & BM_DRAM_CTL84_ODT_WR_MAP_CS2) +#define BP_DRAM_CTL84_RSVD2 12 +#define BM_DRAM_CTL84_RSVD2 0x0000F000 +#define BF_DRAM_CTL84_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL84_RSVD2) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS1 8 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS1 0x00000F00 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS1(v) \ + (((v) << 8) & BM_DRAM_CTL84_ODT_WR_MAP_CS1) +#define BP_DRAM_CTL84_RSVD1 4 +#define BM_DRAM_CTL84_RSVD1 0x000000F0 +#define BF_DRAM_CTL84_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL84_RSVD1) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS0 0 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS0 0x0000000F +#define BF_DRAM_CTL84_ODT_WR_MAP_CS0(v) \ + (((v) << 0) & BM_DRAM_CTL84_ODT_WR_MAP_CS0) + +#define HW_DRAM_CTL85 (0x00000154) + +#define BP_DRAM_CTL85_PAD_CTRL_REG_0 0 +#define BM_DRAM_CTL85_PAD_CTRL_REG_0 0xFFFFFFFF +#define BF_DRAM_CTL85_PAD_CTRL_REG_0(v) (v) + +#define HW_DRAM_CTL86 (0x00000158) + +#define BP_DRAM_CTL86_OBSOLETE 16 +#define BM_DRAM_CTL86_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL86_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL86_OBSOLETE) +#define BP_DRAM_CTL86_VERSION 0 +#define BM_DRAM_CTL86_VERSION 0x0000FFFF +#define BF_DRAM_CTL86_VERSION(v) \ + (((v) << 0) & BM_DRAM_CTL86_VERSION) + +#define HW_DRAM_CTL87 (0x0000015c) + +#define BP_DRAM_CTL87_DLL_CTRL_REG_0_0 0 +#define BM_DRAM_CTL87_DLL_CTRL_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL87_DLL_CTRL_REG_0_0(v) (v) + +#define HW_DRAM_CTL88 (0x00000160) + +#define BP_DRAM_CTL88_DLL_CTRL_REG_0_1 0 +#define BM_DRAM_CTL88_DLL_CTRL_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL88_DLL_CTRL_REG_0_1(v) (v) + +#define HW_DRAM_CTL89 (0x00000164) + +#define BP_DRAM_CTL89_DLL_CTRL_REG_0_2 0 +#define BM_DRAM_CTL89_DLL_CTRL_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL89_DLL_CTRL_REG_0_2(v) (v) + +#define HW_DRAM_CTL90 (0x00000168) + +#define BP_DRAM_CTL90_DLL_CTRL_REG_0_3 0 +#define BM_DRAM_CTL90_DLL_CTRL_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL90_DLL_CTRL_REG_0_3(v) (v) + +#define HW_DRAM_CTL91 (0x0000016c) + +#define BP_DRAM_CTL91_DLL_CTRL_REG_1_0 0 +#define BM_DRAM_CTL91_DLL_CTRL_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL91_DLL_CTRL_REG_1_0(v) (v) + +#define HW_DRAM_CTL92 (0x00000170) + +#define BP_DRAM_CTL92_DLL_CTRL_REG_1_1 0 +#define BM_DRAM_CTL92_DLL_CTRL_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL92_DLL_CTRL_REG_1_1(v) (v) + +#define HW_DRAM_CTL93 (0x00000174) + +#define BP_DRAM_CTL93_DLL_CTRL_REG_1_2 0 +#define BM_DRAM_CTL93_DLL_CTRL_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL93_DLL_CTRL_REG_1_2(v) (v) + +#define HW_DRAM_CTL94 (0x00000178) + +#define BP_DRAM_CTL94_DLL_CTRL_REG_1_3 0 +#define BM_DRAM_CTL94_DLL_CTRL_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL94_DLL_CTRL_REG_1_3(v) (v) + +#define HW_DRAM_CTL95 (0x0000017c) + +#define BP_DRAM_CTL95_DLL_OBS_REG_0_0 0 +#define BM_DRAM_CTL95_DLL_OBS_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL95_DLL_OBS_REG_0_0(v) (v) + +#define HW_DRAM_CTL96 (0x00000180) + +#define BP_DRAM_CTL96_DLL_OBS_REG_0_1 0 +#define BM_DRAM_CTL96_DLL_OBS_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL96_DLL_OBS_REG_0_1(v) (v) + +#define HW_DRAM_CTL97 (0x00000184) + +#define BP_DRAM_CTL97_DLL_OBS_REG_0_2 0 +#define BM_DRAM_CTL97_DLL_OBS_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL97_DLL_OBS_REG_0_2(v) (v) + +#define HW_DRAM_CTL98 (0x00000188) + +#define BP_DRAM_CTL98_DLL_OBS_REG_0_3 0 +#define BM_DRAM_CTL98_DLL_OBS_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL98_DLL_OBS_REG_0_3(v) (v) + +#define HW_DRAM_CTL99 (0x0000018c) + +#define BP_DRAM_CTL99_PHY_OBS_REG_0_0 0 +#define BM_DRAM_CTL99_PHY_OBS_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL99_PHY_OBS_REG_0_0(v) (v) + +#define HW_DRAM_CTL100 (0x00000190) + +#define BP_DRAM_CTL100_PHY_OBS_REG_0_1 0 +#define BM_DRAM_CTL100_PHY_OBS_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL100_PHY_OBS_REG_0_1(v) (v) + +#define HW_DRAM_CTL101 (0x00000194) + +#define BP_DRAM_CTL101_PHY_OBS_REG_0_2 0 +#define BM_DRAM_CTL101_PHY_OBS_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL101_PHY_OBS_REG_0_2(v) (v) + +#define HW_DRAM_CTL102 (0x00000198) + +#define BP_DRAM_CTL102_PHY_OBS_REG_0_3 0 +#define BM_DRAM_CTL102_PHY_OBS_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL102_PHY_OBS_REG_0_3(v) (v) + +#define HW_DRAM_CTL103 (0x0000019c) + +#define BP_DRAM_CTL103_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL103_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL103_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL104 (0x000001a0) + +#define BP_DRAM_CTL104_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL104_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL104_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL105 (0x000001a4) + +#define BP_DRAM_CTL105_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL105_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL105_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL106 (0x000001a8) + +#define BP_DRAM_CTL106_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL106_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL106_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL107 (0x000001ac) + +#define BP_DRAM_CTL107_OBSOLETE 16 +#define BM_DRAM_CTL107_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL107_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL107_OBSOLETE) +#define BP_DRAM_CTL107_RSVD1 9 +#define BM_DRAM_CTL107_RSVD1 0x0000FE00 +#define BF_DRAM_CTL107_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL107_RSVD1) +#define BP_DRAM_CTL107_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL107_DLL_OBS_REG_1_0 0x000001FF +#define BF_DRAM_CTL107_DLL_OBS_REG_1_0(v) \ + (((v) << 0) & BM_DRAM_CTL107_DLL_OBS_REG_1_0) + +#define HW_DRAM_CTL108 (0x000001b0) + +#define BP_DRAM_CTL108_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL108_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL108_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL109 (0x000001b4) + +#define BP_DRAM_CTL109_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL109_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL109_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL110 (0x000001b8) + +#define BP_DRAM_CTL110_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL110_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL110_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL111 (0x000001bc) + +#define BP_DRAM_CTL111_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL111_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL111_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL112 (0x000001c0) + +#define BP_DRAM_CTL112_OBSOLETE 16 +#define BM_DRAM_CTL112_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL112_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL112_OBSOLETE) +#define BP_DRAM_CTL112_RSVD1 9 +#define BM_DRAM_CTL112_RSVD1 0x0000FE00 +#define BF_DRAM_CTL112_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL112_RSVD1) +#define BP_DRAM_CTL112_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL112_DLL_OBS_REG_1_1 0x000001FF +#define BF_DRAM_CTL112_DLL_OBS_REG_1_1(v) \ + (((v) << 0) & BM_DRAM_CTL112_DLL_OBS_REG_1_1) + +#define HW_DRAM_CTL113 (0x000001c4) + +#define BP_DRAM_CTL113_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL113_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL113_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL114 (0x000001c8) + +#define BP_DRAM_CTL114_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL114_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL114_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL115 (0x000001cc) + +#define BP_DRAM_CTL115_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL115_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL115_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL116 (0x000001d0) + +#define BP_DRAM_CTL116_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL116_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL116_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL117 (0x000001d4) + +#define BP_DRAM_CTL117_OBSOLETE 16 +#define BM_DRAM_CTL117_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL117_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL117_OBSOLETE) +#define BP_DRAM_CTL117_RSVD1 9 +#define BM_DRAM_CTL117_RSVD1 0x0000FE00 +#define BF_DRAM_CTL117_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL117_RSVD1) +#define BP_DRAM_CTL117_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL117_DLL_OBS_REG_1_2 0x000001FF +#define BF_DRAM_CTL117_DLL_OBS_REG_1_2(v) \ + (((v) << 0) & BM_DRAM_CTL117_DLL_OBS_REG_1_2) + +#define HW_DRAM_CTL118 (0x000001d8) + +#define BP_DRAM_CTL118_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL118_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL118_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL119 (0x000001dc) + +#define BP_DRAM_CTL119_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL119_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL119_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL120 (0x000001e0) + +#define BP_DRAM_CTL120_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL120_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL120_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL121 (0x000001e4) + +#define BP_DRAM_CTL121_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL121_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL121_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL122 (0x000001e8) + +#define BP_DRAM_CTL122_OBSOLETE 16 +#define BM_DRAM_CTL122_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL122_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL122_OBSOLETE) +#define BP_DRAM_CTL122_RSVD1 9 +#define BM_DRAM_CTL122_RSVD1 0x0000FE00 +#define BF_DRAM_CTL122_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL122_RSVD1) +#define BP_DRAM_CTL122_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL122_DLL_OBS_REG_1_3 0x000001FF +#define BF_DRAM_CTL122_DLL_OBS_REG_1_3(v) \ + (((v) << 0) & BM_DRAM_CTL122_DLL_OBS_REG_1_3) + +#define HW_DRAM_CTL123 (0x000001ec) + +#define BP_DRAM_CTL123_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL123_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL123_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL124 (0x000001f0) + +#define BP_DRAM_CTL124_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL124_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL124_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL125 (0x000001f4) + +#define BP_DRAM_CTL125_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL125_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL125_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL126 (0x000001f8) + +#define BP_DRAM_CTL126_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL126_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL126_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL127 (0x000001fc) + +#define BP_DRAM_CTL127_OBSOLETE 16 +#define BM_DRAM_CTL127_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL127_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL127_OBSOLETE) +#define BP_DRAM_CTL127_RSVD1 9 +#define BM_DRAM_CTL127_RSVD1 0x0000FE00 +#define BF_DRAM_CTL127_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL127_RSVD1) +#define BP_DRAM_CTL127_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL127_DLL_OBS_REG_2_0 0x000001FF +#define BF_DRAM_CTL127_DLL_OBS_REG_2_0(v) \ + (((v) << 0) & BM_DRAM_CTL127_DLL_OBS_REG_2_0) + +#define HW_DRAM_CTL128 (0x00000200) + +#define BP_DRAM_CTL128_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL128_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL128_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL129 (0x00000204) + +#define BP_DRAM_CTL129_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL129_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL129_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL130 (0x00000208) + +#define BP_DRAM_CTL130_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL130_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL130_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL131 (0x0000020c) + +#define BP_DRAM_CTL131_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL131_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL131_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL132 (0x00000210) + +#define BP_DRAM_CTL132_OBSOLETE 16 +#define BM_DRAM_CTL132_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL132_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL132_OBSOLETE) +#define BP_DRAM_CTL132_RSVD1 9 +#define BM_DRAM_CTL132_RSVD1 0x0000FE00 +#define BF_DRAM_CTL132_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL132_RSVD1) +#define BP_DRAM_CTL132_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL132_DLL_OBS_REG_2_1 0x000001FF +#define BF_DRAM_CTL132_DLL_OBS_REG_2_1(v) \ + (((v) << 0) & BM_DRAM_CTL132_DLL_OBS_REG_2_1) + +#define HW_DRAM_CTL133 (0x00000214) + +#define BP_DRAM_CTL133_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL133_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL133_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL134 (0x00000218) + +#define BP_DRAM_CTL134_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL134_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL134_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL135 (0x0000021c) + +#define BP_DRAM_CTL135_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL135_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL135_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL136 (0x00000220) + +#define BP_DRAM_CTL136_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL136_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL136_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL137 (0x00000224) + +#define BP_DRAM_CTL137_OBSOLETE 16 +#define BM_DRAM_CTL137_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL137_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL137_OBSOLETE) +#define BP_DRAM_CTL137_RSVD1 9 +#define BM_DRAM_CTL137_RSVD1 0x0000FE00 +#define BF_DRAM_CTL137_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL137_RSVD1) +#define BP_DRAM_CTL137_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL137_DLL_OBS_REG_2_2 0x000001FF +#define BF_DRAM_CTL137_DLL_OBS_REG_2_2(v) \ + (((v) << 0) & BM_DRAM_CTL137_DLL_OBS_REG_2_2) + +#define HW_DRAM_CTL138 (0x00000228) + +#define BP_DRAM_CTL138_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL138_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL138_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL139 (0x0000022c) + +#define BP_DRAM_CTL139_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL139_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL139_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL140 (0x00000230) + +#define BP_DRAM_CTL140_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL140_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL140_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL141 (0x00000234) + +#define BP_DRAM_CTL141_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL141_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL141_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL142 (0x00000238) + +#define BP_DRAM_CTL142_OBSOLETE 16 +#define BM_DRAM_CTL142_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL142_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL142_OBSOLETE) +#define BP_DRAM_CTL142_RSVD1 9 +#define BM_DRAM_CTL142_RSVD1 0x0000FE00 +#define BF_DRAM_CTL142_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL142_RSVD1) +#define BP_DRAM_CTL142_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL142_DLL_OBS_REG_2_3 0x000001FF +#define BF_DRAM_CTL142_DLL_OBS_REG_2_3(v) \ + (((v) << 0) & BM_DRAM_CTL142_DLL_OBS_REG_2_3) + +#define HW_DRAM_CTL143 (0x0000023c) + +#define BP_DRAM_CTL143_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL143_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL143_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL144 (0x00000240) + +#define BP_DRAM_CTL144_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL144_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL144_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL145 (0x00000244) + +#define BP_DRAM_CTL145_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL145_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL145_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL146 (0x00000248) + +#define BP_DRAM_CTL146_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL146_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL146_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL147 (0x0000024c) + +#define BP_DRAM_CTL147_OBSOLETE 16 +#define BM_DRAM_CTL147_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL147_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL147_OBSOLETE) +#define BP_DRAM_CTL147_RSVD1 9 +#define BM_DRAM_CTL147_RSVD1 0x0000FE00 +#define BF_DRAM_CTL147_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL147_RSVD1) +#define BP_DRAM_CTL147_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL147_DLL_OBS_REG_3_0 0x000001FF +#define BF_DRAM_CTL147_DLL_OBS_REG_3_0(v) \ + (((v) << 0) & BM_DRAM_CTL147_DLL_OBS_REG_3_0) + +#define HW_DRAM_CTL148 (0x00000250) + +#define BP_DRAM_CTL148_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL148_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL148_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL149 (0x00000254) + +#define BP_DRAM_CTL149_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL149_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL149_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL150 (0x00000258) + +#define BP_DRAM_CTL150_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL150_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL150_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL151 (0x0000025c) + +#define BP_DRAM_CTL151_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL151_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL151_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL152 (0x00000260) + +#define BP_DRAM_CTL152_OBSOLETE 16 +#define BM_DRAM_CTL152_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL152_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL152_OBSOLETE) +#define BP_DRAM_CTL152_RSVD1 9 +#define BM_DRAM_CTL152_RSVD1 0x0000FE00 +#define BF_DRAM_CTL152_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL152_RSVD1) +#define BP_DRAM_CTL152_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL152_DLL_OBS_REG_3_1 0x000001FF +#define BF_DRAM_CTL152_DLL_OBS_REG_3_1(v) \ + (((v) << 0) & BM_DRAM_CTL152_DLL_OBS_REG_3_1) + +#define HW_DRAM_CTL153 (0x00000264) + +#define BP_DRAM_CTL153_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL153_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL153_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL154 (0x00000268) + +#define BP_DRAM_CTL154_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL154_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL154_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL155 (0x0000026c) + +#define BP_DRAM_CTL155_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL155_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL155_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL156 (0x00000270) + +#define BP_DRAM_CTL156_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL156_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL156_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL157 (0x00000274) + +#define BP_DRAM_CTL157_OBSOLETE 16 +#define BM_DRAM_CTL157_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL157_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL157_OBSOLETE) +#define BP_DRAM_CTL157_RSVD1 9 +#define BM_DRAM_CTL157_RSVD1 0x0000FE00 +#define BF_DRAM_CTL157_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL157_RSVD1) +#define BP_DRAM_CTL157_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL157_DLL_OBS_REG_3_2 0x000001FF +#define BF_DRAM_CTL157_DLL_OBS_REG_3_2(v) \ + (((v) << 0) & BM_DRAM_CTL157_DLL_OBS_REG_3_2) + +#define HW_DRAM_CTL158 (0x00000278) + +#define BP_DRAM_CTL158_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL158_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL158_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL159 (0x0000027c) + +#define BP_DRAM_CTL159_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL159_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL159_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL160 (0x00000280) + +#define BP_DRAM_CTL160_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL160_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL160_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL161 (0x00000284) + +#define BP_DRAM_CTL161_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL161_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL161_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL162 (0x00000288) + +#define BP_DRAM_CTL162_RSVD3 27 +#define BM_DRAM_CTL162_RSVD3 0xF8000000 +#define BF_DRAM_CTL162_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL162_RSVD3) +#define BP_DRAM_CTL162_W2R_SAMECS_DLY 24 +#define BM_DRAM_CTL162_W2R_SAMECS_DLY 0x07000000 +#define BF_DRAM_CTL162_W2R_SAMECS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL162_W2R_SAMECS_DLY) +#define BP_DRAM_CTL162_RSVD2 19 +#define BM_DRAM_CTL162_RSVD2 0x00F80000 +#define BF_DRAM_CTL162_RSVD2(v) \ + (((v) << 19) & BM_DRAM_CTL162_RSVD2) +#define BP_DRAM_CTL162_W2R_DIFFCS_DLY 16 +#define BM_DRAM_CTL162_W2R_DIFFCS_DLY 0x00070000 +#define BF_DRAM_CTL162_W2R_DIFFCS_DLY(v) \ + (((v) << 16) & BM_DRAM_CTL162_W2R_DIFFCS_DLY) +#define BP_DRAM_CTL162_RSVD1 9 +#define BM_DRAM_CTL162_RSVD1 0x0000FE00 +#define BF_DRAM_CTL162_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL162_RSVD1) +#define BP_DRAM_CTL162_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL162_DLL_OBS_REG_3_3 0x000001FF +#define BF_DRAM_CTL162_DLL_OBS_REG_3_3(v) \ + (((v) << 0) & BM_DRAM_CTL162_DLL_OBS_REG_3_3) + +#define HW_DRAM_CTL163 (0x0000028c) + +#define BP_DRAM_CTL163_DLL_RST_ADJ_DLY 24 +#define BM_DRAM_CTL163_DLL_RST_ADJ_DLY 0xFF000000 +#define BF_DRAM_CTL163_DLL_RST_ADJ_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL163_DLL_RST_ADJ_DLY) +#define BP_DRAM_CTL163_RSVD3 20 +#define BM_DRAM_CTL163_RSVD3 0x00F00000 +#define BF_DRAM_CTL163_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL163_RSVD3) +#define BP_DRAM_CTL163_WRLAT_ADJ 16 +#define BM_DRAM_CTL163_WRLAT_ADJ 0x000F0000 +#define BF_DRAM_CTL163_WRLAT_ADJ(v) \ + (((v) << 16) & BM_DRAM_CTL163_WRLAT_ADJ) +#define BP_DRAM_CTL163_RSVD2 12 +#define BM_DRAM_CTL163_RSVD2 0x0000F000 +#define BF_DRAM_CTL163_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL163_RSVD2) +#define BP_DRAM_CTL163_RDLAT_ADJ 8 +#define BM_DRAM_CTL163_RDLAT_ADJ 0x00000F00 +#define BF_DRAM_CTL163_RDLAT_ADJ(v) \ + (((v) << 8) & BM_DRAM_CTL163_RDLAT_ADJ) +#define BP_DRAM_CTL163_RSVD1 4 +#define BM_DRAM_CTL163_RSVD1 0x000000F0 +#define BF_DRAM_CTL163_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL163_RSVD1) +#define BP_DRAM_CTL163_DRAM_CLASS 0 +#define BM_DRAM_CTL163_DRAM_CLASS 0x0000000F +#define BF_DRAM_CTL163_DRAM_CLASS(v) \ + (((v) << 0) & BM_DRAM_CTL163_DRAM_CLASS) + +#define HW_DRAM_CTL164 (0x00000290) + +#define BP_DRAM_CTL164_OBSOLETE 24 +#define BM_DRAM_CTL164_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL164_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL164_OBSOLETE) +#define BP_DRAM_CTL164_RSVD1 18 +#define BM_DRAM_CTL164_RSVD1 0x00FC0000 +#define BF_DRAM_CTL164_RSVD1(v) \ + (((v) << 18) & BM_DRAM_CTL164_RSVD1) +#define BP_DRAM_CTL164_INT_ACK 8 +#define BM_DRAM_CTL164_INT_ACK 0x0003FF00 +#define BF_DRAM_CTL164_INT_ACK(v) \ + (((v) << 8) & BM_DRAM_CTL164_INT_ACK) +#define BP_DRAM_CTL164_TMOD 0 +#define BM_DRAM_CTL164_TMOD 0x000000FF +#define BF_DRAM_CTL164_TMOD(v) \ + (((v) << 0) & BM_DRAM_CTL164_TMOD) + +#define HW_DRAM_CTL171 (0x000002ac) + +#define BP_DRAM_CTL171_RSVD2 25 +#define BM_DRAM_CTL171_RSVD2 0xFE000000 +#define BF_DRAM_CTL171_RSVD2(v) \ + (((v) << 25) & BM_DRAM_CTL171_RSVD2) +#define BM_DRAM_CTL171_AXI5_BDW_OVFLOW 0x01000000 +#define BP_DRAM_CTL171_RSVD1 17 +#define BM_DRAM_CTL171_RSVD1 0x00FE0000 +#define BF_DRAM_CTL171_RSVD1(v) \ + (((v) << 17) & BM_DRAM_CTL171_RSVD1) +#define BM_DRAM_CTL171_AXI4_BDW_OVFLOW 0x00010000 +#define BP_DRAM_CTL171_DLL_RST_DELAY 0 +#define BM_DRAM_CTL171_DLL_RST_DELAY 0x0000FFFF +#define BF_DRAM_CTL171_DLL_RST_DELAY(v) \ + (((v) << 0) & BM_DRAM_CTL171_DLL_RST_DELAY) + +#define HW_DRAM_CTL172 (0x000002b0) + +#define BP_DRAM_CTL172_RSVD4 25 +#define BM_DRAM_CTL172_RSVD4 0xFE000000 +#define BF_DRAM_CTL172_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL172_RSVD4) +#define BM_DRAM_CTL172_RESYNC_DLL_PER_AREF_EN 0x01000000 +#define BP_DRAM_CTL172_RSVD3 17 +#define BM_DRAM_CTL172_RSVD3 0x00FE0000 +#define BF_DRAM_CTL172_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL172_RSVD3) +#define BM_DRAM_CTL172_RESYNC_DLL 0x00010000 +#define BP_DRAM_CTL172_RSVD2 9 +#define BM_DRAM_CTL172_RSVD2 0x0000FE00 +#define BF_DRAM_CTL172_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL172_RSVD2) +#define BM_DRAM_CTL172_CONCURRENTAP_WR_ONLY 0x00000100 +#define BP_DRAM_CTL172_RSVD1 1 +#define BM_DRAM_CTL172_RSVD1 0x000000FE +#define BF_DRAM_CTL172_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL172_RSVD1) +#define BM_DRAM_CTL172_CKE_STATUS 0x00000001 + +#define HW_DRAM_CTL173 (0x000002b4) + +#define BP_DRAM_CTL173_RSVD4 27 +#define BM_DRAM_CTL173_RSVD4 0xF8000000 +#define BF_DRAM_CTL173_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL173_RSVD4) +#define BP_DRAM_CTL173_AXI4_W_PRIORITY 24 +#define BM_DRAM_CTL173_AXI4_W_PRIORITY 0x07000000 +#define BF_DRAM_CTL173_AXI4_W_PRIORITY(v) \ + (((v) << 24) & BM_DRAM_CTL173_AXI4_W_PRIORITY) +#define BP_DRAM_CTL173_RSVD3 19 +#define BM_DRAM_CTL173_RSVD3 0x00F80000 +#define BF_DRAM_CTL173_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL173_RSVD3) +#define BP_DRAM_CTL173_AXI4_R_PRIORITY 16 +#define BM_DRAM_CTL173_AXI4_R_PRIORITY 0x00070000 +#define BF_DRAM_CTL173_AXI4_R_PRIORITY(v) \ + (((v) << 16) & BM_DRAM_CTL173_AXI4_R_PRIORITY) +#define BP_DRAM_CTL173_RSVD2 10 +#define BM_DRAM_CTL173_RSVD2 0x0000FC00 +#define BF_DRAM_CTL173_RSVD2(v) \ + (((v) << 10) & BM_DRAM_CTL173_RSVD2) +#define BP_DRAM_CTL173_AXI5_FIFO_TYPE_REG 8 +#define BM_DRAM_CTL173_AXI5_FIFO_TYPE_REG 0x00000300 +#define BF_DRAM_CTL173_AXI5_FIFO_TYPE_REG(v) \ + (((v) << 8) & BM_DRAM_CTL173_AXI5_FIFO_TYPE_REG) +#define BP_DRAM_CTL173_RSVD1 2 +#define BM_DRAM_CTL173_RSVD1 0x000000FC +#define BF_DRAM_CTL173_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL173_RSVD1) +#define BP_DRAM_CTL173_AXI4_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL173_AXI4_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL173_AXI4_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL173_AXI4_FIFO_TYPE_REG) + +#define HW_DRAM_CTL174 (0x000002b8) + +#define BP_DRAM_CTL174_RSVD4 27 +#define BM_DRAM_CTL174_RSVD4 0xF8000000 +#define BF_DRAM_CTL174_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL174_RSVD4) +#define BP_DRAM_CTL174_R2R_SAMECS_DLY 24 +#define BM_DRAM_CTL174_R2R_SAMECS_DLY 0x07000000 +#define BF_DRAM_CTL174_R2R_SAMECS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL174_R2R_SAMECS_DLY) +#define BP_DRAM_CTL174_RSVD3 19 +#define BM_DRAM_CTL174_RSVD3 0x00F80000 +#define BF_DRAM_CTL174_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL174_RSVD3) +#define BP_DRAM_CTL174_R2R_DIFFCS_DLY 16 +#define BM_DRAM_CTL174_R2R_DIFFCS_DLY 0x00070000 +#define BF_DRAM_CTL174_R2R_DIFFCS_DLY(v) \ + (((v) << 16) & BM_DRAM_CTL174_R2R_DIFFCS_DLY) +#define BP_DRAM_CTL174_RSVD2 11 +#define BM_DRAM_CTL174_RSVD2 0x0000F800 +#define BF_DRAM_CTL174_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL174_RSVD2) +#define BP_DRAM_CTL174_AXI5_W_PRIORITY 8 +#define BM_DRAM_CTL174_AXI5_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL174_AXI5_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL174_AXI5_W_PRIORITY) +#define BP_DRAM_CTL174_RSVD1 3 +#define BM_DRAM_CTL174_RSVD1 0x000000F8 +#define BF_DRAM_CTL174_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL174_RSVD1) +#define BP_DRAM_CTL174_AXI5_R_PRIORITY 0 +#define BM_DRAM_CTL174_AXI5_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL174_AXI5_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL174_AXI5_R_PRIORITY) + +#define HW_DRAM_CTL175 (0x000002bc) + +#define BP_DRAM_CTL175_RSVD4 27 +#define BM_DRAM_CTL175_RSVD4 0xF8000000 +#define BF_DRAM_CTL175_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL175_RSVD4) +#define BP_DRAM_CTL175_W2W_DIFFCS_DLY 24 +#define BM_DRAM_CTL175_W2W_DIFFCS_DLY 0x07000000 +#define BF_DRAM_CTL175_W2W_DIFFCS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL175_W2W_DIFFCS_DLY) +#define BP_DRAM_CTL175_RSVD3 19 +#define BM_DRAM_CTL175_RSVD3 0x00F80000 +#define BF_DRAM_CTL175_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL175_RSVD3) +#define BP_DRAM_CTL175_TBST_INT_INTERVAL 16 +#define BM_DRAM_CTL175_TBST_INT_INTERVAL 0x00070000 +#define BF_DRAM_CTL175_TBST_INT_INTERVAL(v) \ + (((v) << 16) & BM_DRAM_CTL175_TBST_INT_INTERVAL) +#define BP_DRAM_CTL175_RSVD2 11 +#define BM_DRAM_CTL175_RSVD2 0x0000F800 +#define BF_DRAM_CTL175_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL175_RSVD2) +#define BP_DRAM_CTL175_R2W_SAMECS_DLY 8 +#define BM_DRAM_CTL175_R2W_SAMECS_DLY 0x00000700 +#define BF_DRAM_CTL175_R2W_SAMECS_DLY(v) \ + (((v) << 8) & BM_DRAM_CTL175_R2W_SAMECS_DLY) +#define BP_DRAM_CTL175_RSVD1 3 +#define BM_DRAM_CTL175_RSVD1 0x000000F8 +#define BF_DRAM_CTL175_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL175_RSVD1) +#define BP_DRAM_CTL175_R2W_DIFFCS_DLY 0 +#define BM_DRAM_CTL175_R2W_DIFFCS_DLY 0x00000007 +#define BF_DRAM_CTL175_R2W_DIFFCS_DLY(v) \ + (((v) << 0) & BM_DRAM_CTL175_R2W_DIFFCS_DLY) + +#define HW_DRAM_CTL176 (0x000002c0) + +#define BP_DRAM_CTL176_RSVD4 28 +#define BM_DRAM_CTL176_RSVD4 0xF0000000 +#define BF_DRAM_CTL176_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL176_RSVD4) +#define BP_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS 24 +#define BM_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS 0x0F000000 +#define BF_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS(v) \ + (((v) << 24) & BM_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS) +#define BP_DRAM_CTL176_RSVD3 20 +#define BM_DRAM_CTL176_RSVD3 0x00F00000 +#define BF_DRAM_CTL176_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL176_RSVD3) +#define BP_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS 16 +#define BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS 0x000F0000 +#define BF_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS(v) \ + (((v) << 16) & BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS) +#define BP_DRAM_CTL176_RSVD2 12 +#define BM_DRAM_CTL176_RSVD2 0x0000F000 +#define BF_DRAM_CTL176_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL176_RSVD2) +#define BP_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS 8 +#define BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS 0x00000F00 +#define BF_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS(v) \ + (((v) << 8) & BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS) +#define BP_DRAM_CTL176_RSVD1 3 +#define BM_DRAM_CTL176_RSVD1 0x000000F8 +#define BF_DRAM_CTL176_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL176_RSVD1) +#define BP_DRAM_CTL176_W2W_SAMECS_DLY 0 +#define BM_DRAM_CTL176_W2W_SAMECS_DLY 0x00000007 +#define BF_DRAM_CTL176_W2W_SAMECS_DLY(v) \ + (((v) << 0) & BM_DRAM_CTL176_W2W_SAMECS_DLY) + +#define HW_DRAM_CTL177 (0x000002c4) + +#define BP_DRAM_CTL177_RSVD4 29 +#define BM_DRAM_CTL177_RSVD4 0xE0000000 +#define BF_DRAM_CTL177_RSVD4(v) \ + (((v) << 29) & BM_DRAM_CTL177_RSVD4) +#define BP_DRAM_CTL177_TCCD 24 +#define BM_DRAM_CTL177_TCCD 0x1F000000 +#define BF_DRAM_CTL177_TCCD(v) \ + (((v) << 24) & BM_DRAM_CTL177_TCCD) +#define BP_DRAM_CTL177_RSVD3 20 +#define BM_DRAM_CTL177_RSVD3 0x00F00000 +#define BF_DRAM_CTL177_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL177_RSVD3) +#define BP_DRAM_CTL177_TRP_AB 16 +#define BM_DRAM_CTL177_TRP_AB 0x000F0000 +#define BF_DRAM_CTL177_TRP_AB(v) \ + (((v) << 16) & BM_DRAM_CTL177_TRP_AB) +#define BP_DRAM_CTL177_RSVD2 12 +#define BM_DRAM_CTL177_RSVD2 0x0000F000 +#define BF_DRAM_CTL177_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL177_RSVD2) +#define BP_DRAM_CTL177_CKSRX 8 +#define BM_DRAM_CTL177_CKSRX 0x00000F00 +#define BF_DRAM_CTL177_CKSRX(v) \ + (((v) << 8) & BM_DRAM_CTL177_CKSRX) +#define BP_DRAM_CTL177_RSVD1 4 +#define BM_DRAM_CTL177_RSVD1 0x000000F0 +#define BF_DRAM_CTL177_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL177_RSVD1) +#define BP_DRAM_CTL177_CKSRE 0 +#define BM_DRAM_CTL177_CKSRE 0x0000000F +#define BF_DRAM_CTL177_CKSRE(v) \ + (((v) << 0) & BM_DRAM_CTL177_CKSRE) + +#define HW_DRAM_CTL178 (0x000002c8) + +#define BM_DRAM_CTL178_RSVD4 0x80000000 +#define BP_DRAM_CTL178_AXI5_BDW 24 +#define BM_DRAM_CTL178_AXI5_BDW 0x7F000000 +#define BF_DRAM_CTL178_AXI5_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL178_AXI5_BDW) +#define BM_DRAM_CTL178_RSVD3 0x00800000 +#define BP_DRAM_CTL178_AXI4_CURRENT_BDW 16 +#define BM_DRAM_CTL178_AXI4_CURRENT_BDW 0x007F0000 +#define BF_DRAM_CTL178_AXI4_CURRENT_BDW(v) \ + (((v) << 16) & BM_DRAM_CTL178_AXI4_CURRENT_BDW) +#define BM_DRAM_CTL178_RSVD2 0x00008000 +#define BP_DRAM_CTL178_AXI4_BDW 8 +#define BM_DRAM_CTL178_AXI4_BDW 0x00007F00 +#define BF_DRAM_CTL178_AXI4_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL178_AXI4_BDW) +#define BP_DRAM_CTL178_RSVD1 5 +#define BM_DRAM_CTL178_RSVD1 0x000000E0 +#define BF_DRAM_CTL178_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL178_RSVD1) +#define BP_DRAM_CTL178_TCKESR 0 +#define BM_DRAM_CTL178_TCKESR 0x0000001F +#define BF_DRAM_CTL178_TCKESR(v) \ + (((v) << 0) & BM_DRAM_CTL178_TCKESR) + +#define HW_DRAM_CTL179 (0x000002cc) + +#define BP_DRAM_CTL179_RSVD3 24 +#define BM_DRAM_CTL179_RSVD3 0xFF000000 +#define BF_DRAM_CTL179_RSVD3(v) \ + (((v) << 24) & BM_DRAM_CTL179_RSVD3) +#define BP_DRAM_CTL179_RSVD2 22 +#define BM_DRAM_CTL179_RSVD2 0x00C00000 +#define BF_DRAM_CTL179_RSVD2(v) \ + (((v) << 22) & BM_DRAM_CTL179_RSVD2) +#define BP_DRAM_CTL179_TDFI_PHYUPD_TYPE1 8 +#define BM_DRAM_CTL179_TDFI_PHYUPD_TYPE1 0x003FFF00 +#define BF_DRAM_CTL179_TDFI_PHYUPD_TYPE1(v) \ + (((v) << 8) & BM_DRAM_CTL179_TDFI_PHYUPD_TYPE1) +#define BM_DRAM_CTL179_RSVD1 0x00000080 +#define BP_DRAM_CTL179_AXI5_CURRENT_BDW 0 +#define BM_DRAM_CTL179_AXI5_CURRENT_BDW 0x0000007F +#define BF_DRAM_CTL179_AXI5_CURRENT_BDW(v) \ + (((v) << 0) & BM_DRAM_CTL179_AXI5_CURRENT_BDW) + +#define HW_DRAM_CTL180 (0x000002d0) + +#define BP_DRAM_CTL180_RSVD2 30 +#define BM_DRAM_CTL180_RSVD2 0xC0000000 +#define BF_DRAM_CTL180_RSVD2(v) \ + (((v) << 30) & BM_DRAM_CTL180_RSVD2) +#define BP_DRAM_CTL180_TDFI_PHYUPD_TYPE3 16 +#define BM_DRAM_CTL180_TDFI_PHYUPD_TYPE3 0x3FFF0000 +#define BF_DRAM_CTL180_TDFI_PHYUPD_TYPE3(v) \ + (((v) << 16) & BM_DRAM_CTL180_TDFI_PHYUPD_TYPE3) +#define BP_DRAM_CTL180_RSVD1 14 +#define BM_DRAM_CTL180_RSVD1 0x0000C000 +#define BF_DRAM_CTL180_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL180_RSVD1) +#define BP_DRAM_CTL180_TDFI_PHYUPD_TYPE2 0 +#define BM_DRAM_CTL180_TDFI_PHYUPD_TYPE2 0x00003FFF +#define BF_DRAM_CTL180_TDFI_PHYUPD_TYPE2(v) \ + (((v) << 0) & BM_DRAM_CTL180_TDFI_PHYUPD_TYPE2) + +#define HW_DRAM_CTL181 (0x000002d4) + +#define BM_DRAM_CTL181_RSVD2 0x80000000 +#define BP_DRAM_CTL181_MR0_DATA_1 16 +#define BM_DRAM_CTL181_MR0_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL181_MR0_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL181_MR0_DATA_1) +#define BM_DRAM_CTL181_RSVD1 0x00008000 +#define BP_DRAM_CTL181_MR0_DATA_0 0 +#define BM_DRAM_CTL181_MR0_DATA_0 0x00007FFF +#define BF_DRAM_CTL181_MR0_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL181_MR0_DATA_0) + +#define HW_DRAM_CTL182 (0x000002d8) + +#define BM_DRAM_CTL182_RSVD2 0x80000000 +#define BP_DRAM_CTL182_MR0_DATA_3 16 +#define BM_DRAM_CTL182_MR0_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL182_MR0_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL182_MR0_DATA_3) +#define BM_DRAM_CTL182_RSVD1 0x00008000 +#define BP_DRAM_CTL182_MR0_DATA_2 0 +#define BM_DRAM_CTL182_MR0_DATA_2 0x00007FFF +#define BF_DRAM_CTL182_MR0_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL182_MR0_DATA_2) + +#define HW_DRAM_CTL183 (0x000002dc) + +#define BM_DRAM_CTL183_RSVD2 0x80000000 +#define BP_DRAM_CTL183_MR1_DATA_1 16 +#define BM_DRAM_CTL183_MR1_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL183_MR1_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL183_MR1_DATA_1) +#define BM_DRAM_CTL183_RSVD1 0x00008000 +#define BP_DRAM_CTL183_MR1_DATA_0 0 +#define BM_DRAM_CTL183_MR1_DATA_0 0x00007FFF +#define BF_DRAM_CTL183_MR1_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL183_MR1_DATA_0) + +#define HW_DRAM_CTL184 (0x000002e0) + +#define BM_DRAM_CTL184_RSVD2 0x80000000 +#define BP_DRAM_CTL184_MR1_DATA_3 16 +#define BM_DRAM_CTL184_MR1_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL184_MR1_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL184_MR1_DATA_3) +#define BM_DRAM_CTL184_RSVD1 0x00008000 +#define BP_DRAM_CTL184_MR1_DATA_2 0 +#define BM_DRAM_CTL184_MR1_DATA_2 0x00007FFF +#define BF_DRAM_CTL184_MR1_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL184_MR1_DATA_2) + +#define HW_DRAM_CTL185 (0x000002e4) + +#define BM_DRAM_CTL185_RSVD2 0x80000000 +#define BP_DRAM_CTL185_MR2_DATA_1 16 +#define BM_DRAM_CTL185_MR2_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL185_MR2_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL185_MR2_DATA_1) +#define BM_DRAM_CTL185_RSVD1 0x00008000 +#define BP_DRAM_CTL185_MR2_DATA_0 0 +#define BM_DRAM_CTL185_MR2_DATA_0 0x00007FFF +#define BF_DRAM_CTL185_MR2_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL185_MR2_DATA_0) + +#define HW_DRAM_CTL186 (0x000002e8) + +#define BM_DRAM_CTL186_RSVD2 0x80000000 +#define BP_DRAM_CTL186_MR2_DATA_3 16 +#define BM_DRAM_CTL186_MR2_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL186_MR2_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL186_MR2_DATA_3) +#define BM_DRAM_CTL186_RSVD1 0x00008000 +#define BP_DRAM_CTL186_MR2_DATA_2 0 +#define BM_DRAM_CTL186_MR2_DATA_2 0x00007FFF +#define BF_DRAM_CTL186_MR2_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL186_MR2_DATA_2) + +#define HW_DRAM_CTL187 (0x000002ec) + +#define BM_DRAM_CTL187_RSVD2 0x80000000 +#define BP_DRAM_CTL187_MR3_DATA_1 16 +#define BM_DRAM_CTL187_MR3_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL187_MR3_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL187_MR3_DATA_1) +#define BM_DRAM_CTL187_RSVD1 0x00008000 +#define BP_DRAM_CTL187_MR3_DATA_0 0 +#define BM_DRAM_CTL187_MR3_DATA_0 0x00007FFF +#define BF_DRAM_CTL187_MR3_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL187_MR3_DATA_0) + +#define HW_DRAM_CTL188 (0x000002f0) + +#define BM_DRAM_CTL188_RSVD2 0x80000000 +#define BP_DRAM_CTL188_MR3_DATA_3 16 +#define BM_DRAM_CTL188_MR3_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL188_MR3_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL188_MR3_DATA_3) +#define BM_DRAM_CTL188_RSVD1 0x00008000 +#define BP_DRAM_CTL188_MR3_DATA_2 0 +#define BM_DRAM_CTL188_MR3_DATA_2 0x00007FFF +#define BF_DRAM_CTL188_MR3_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL188_MR3_DATA_2) + +#define HW_DRAM_CTL189 (0x000002f4) + +#define BP_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR 0 +#define BM_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR 0x0000FFFF +#define BF_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 0) & BM_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR) +#endif /* __ARCH_ARM___DRAM_H */ diff --git a/arch/arm/mach-mx28/regs-pinctrl.h b/arch/arm/mach-mx28/regs-pinctrl.h new file mode 100644 index 000000000000..03c7f15da080 --- /dev/null +++ b/arch/arm/mach-mx28/regs-pinctrl.h @@ -0,0 +1,2673 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 25 +#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT4 0x01000000 +#define BM_PINCTRL_CTRL_PRESENT3 0x00800000 +#define BM_PINCTRL_CTRL_PRESENT2 0x00400000 +#define BM_PINCTRL_CTRL_PRESENT1 0x00200000 +#define BM_PINCTRL_CTRL_PRESENT0 0x00100000 +#define BP_PINCTRL_CTRL_RSRVD1 5 +#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010 +#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008 +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) + +#define BP_PINCTRL_MUXSEL0_RSRVD0 16 +#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000 +#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) + +#define BP_PINCTRL_MUXSEL1_RSRVD0 26 +#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000 +#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) + +#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_RSRVD0 22 +#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000 +#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) + +#define BP_PINCTRL_MUXSEL5_RSRVD1 24 +#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000 +#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_RSRVD0 12 +#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000 +#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) + +#define BP_PINCTRL_MUXSEL7_RSRVD1 30 +#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000 +#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_RSRVD0 6 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_MUXSEL8 (0x00000180) +#define HW_PINCTRL_MUXSEL8_SET (0x00000184) +#define HW_PINCTRL_MUXSEL8_CLR (0x00000188) +#define HW_PINCTRL_MUXSEL8_TOG (0x0000018c) + +#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00) + +#define HW_PINCTRL_MUXSEL9 (0x00000190) +#define HW_PINCTRL_MUXSEL9_SET (0x00000194) +#define HW_PINCTRL_MUXSEL9_CLR (0x00000198) +#define HW_PINCTRL_MUXSEL9_TOG (0x0000019c) + +#define BP_PINCTRL_MUXSEL9_RSRVD1 10 +#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00 +#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20) +#define BP_PINCTRL_MUXSEL9_RSRVD0 2 +#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC +#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16) + +#define HW_PINCTRL_MUXSEL10 (0x000001a0) +#define HW_PINCTRL_MUXSEL10_SET (0x000001a4) +#define HW_PINCTRL_MUXSEL10_CLR (0x000001a8) +#define HW_PINCTRL_MUXSEL10_TOG (0x000001ac) + +#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00) + +#define HW_PINCTRL_MUXSEL11 (0x000001b0) +#define HW_PINCTRL_MUXSEL11_SET (0x000001b4) +#define HW_PINCTRL_MUXSEL11_CLR (0x000001b8) +#define HW_PINCTRL_MUXSEL11_TOG (0x000001bc) + +#define BP_PINCTRL_MUXSEL11_RSRVD1 22 +#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000 +#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26) +#define BP_PINCTRL_MUXSEL11_RSRVD0 16 +#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000 +#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16) + +#define HW_PINCTRL_MUXSEL12 (0x000001c0) +#define HW_PINCTRL_MUXSEL12_SET (0x000001c4) +#define HW_PINCTRL_MUXSEL12_CLR (0x000001c8) +#define HW_PINCTRL_MUXSEL12_TOG (0x000001cc) + +#define BP_PINCTRL_MUXSEL12_RSRVD0 30 +#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00) + +#define HW_PINCTRL_MUXSEL13 (0x000001d0) +#define HW_PINCTRL_MUXSEL13_SET (0x000001d4) +#define HW_PINCTRL_MUXSEL13_CLR (0x000001d8) +#define HW_PINCTRL_MUXSEL13_TOG (0x000001dc) + +#define BP_PINCTRL_MUXSEL13_RSRVD0 18 +#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000300) +#define HW_PINCTRL_DRIVE0_SET (0x00000304) +#define HW_PINCTRL_DRIVE0_CLR (0x00000308) +#define HW_PINCTRL_DRIVE0_TOG (0x0000030c) + +#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000310) +#define HW_PINCTRL_DRIVE1_SET (0x00000314) +#define HW_PINCTRL_DRIVE1_CLR (0x00000318) +#define HW_PINCTRL_DRIVE1_TOG (0x0000031c) + +#define BP_PINCTRL_DRIVE1_RSRVD0 0 +#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v) + +#define HW_PINCTRL_DRIVE2 (0x00000320) +#define HW_PINCTRL_DRIVE2_SET (0x00000324) +#define HW_PINCTRL_DRIVE2_CLR (0x00000328) +#define HW_PINCTRL_DRIVE2_TOG (0x0000032c) + +#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000330) +#define HW_PINCTRL_DRIVE3_SET (0x00000334) +#define HW_PINCTRL_DRIVE3_CLR (0x00000338) +#define HW_PINCTRL_DRIVE3_TOG (0x0000033c) + +#define BP_PINCTRL_DRIVE3_RSRVD5 20 +#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000340) +#define HW_PINCTRL_DRIVE4_SET (0x00000344) +#define HW_PINCTRL_DRIVE4_CLR (0x00000348) +#define HW_PINCTRL_DRIVE4_TOG (0x0000034c) + +#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000350) +#define HW_PINCTRL_DRIVE5_SET (0x00000354) +#define HW_PINCTRL_DRIVE5_CLR (0x00000358) +#define HW_PINCTRL_DRIVE5_TOG (0x0000035c) + +#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000360) +#define HW_PINCTRL_DRIVE6_SET (0x00000364) +#define HW_PINCTRL_DRIVE6_CLR (0x00000368) +#define HW_PINCTRL_DRIVE6_TOG (0x0000036c) + +#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000370) +#define HW_PINCTRL_DRIVE7_SET (0x00000374) +#define HW_PINCTRL_DRIVE7_CLR (0x00000378) +#define HW_PINCTRL_DRIVE7_TOG (0x0000037c) + +#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA) +#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000380) +#define HW_PINCTRL_DRIVE8_SET (0x00000384) +#define HW_PINCTRL_DRIVE8_CLR (0x00000388) +#define HW_PINCTRL_DRIVE8_TOG (0x0000038c) + +#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000390) +#define HW_PINCTRL_DRIVE9_SET (0x00000394) +#define HW_PINCTRL_DRIVE9_CLR (0x00000398) +#define HW_PINCTRL_DRIVE9_TOG (0x0000039c) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BP_PINCTRL_DRIVE9_RSRVD3 12 +#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE9_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000003a0) +#define HW_PINCTRL_DRIVE10_SET (0x000003a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000003a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000003ac) + +#define BP_PINCTRL_DRIVE10_RSRVD6 24 +#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE10_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000003b0) +#define HW_PINCTRL_DRIVE11_SET (0x000003b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000003b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000003bc) + +#define BP_PINCTRL_DRIVE11_RSRVD4 16 +#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000003c0) +#define HW_PINCTRL_DRIVE12_SET (0x000003c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000003c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000003cc) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000003d0) +#define HW_PINCTRL_DRIVE13_SET (0x000003d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000003d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000003dc) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000003e0) +#define HW_PINCTRL_DRIVE14_SET (0x000003e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000003e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000003ec) + +#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA) +#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BP_PINCTRL_DRIVE14_RSRVD3 12 +#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE14_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_DRIVE15 (0x000003f0) +#define HW_PINCTRL_DRIVE15_SET (0x000003f4) +#define HW_PINCTRL_DRIVE15_CLR (0x000003f8) +#define HW_PINCTRL_DRIVE15_TOG (0x000003fc) + +#define BP_PINCTRL_DRIVE15_RSRVD7 28 +#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE15_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7) +#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA) +#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA) +#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA) +#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA) +#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA) +#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA) +#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA) + +#define HW_PINCTRL_DRIVE16 (0x00000400) +#define HW_PINCTRL_DRIVE16_SET (0x00000404) +#define HW_PINCTRL_DRIVE16_CLR (0x00000408) +#define HW_PINCTRL_DRIVE16_TOG (0x0000040c) + +#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA) +#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA) +#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA) +#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA) +#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA) +#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA) +#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA) +#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA) + +#define HW_PINCTRL_DRIVE17 (0x00000410) +#define HW_PINCTRL_DRIVE17_SET (0x00000414) +#define HW_PINCTRL_DRIVE17_CLR (0x00000418) +#define HW_PINCTRL_DRIVE17_TOG (0x0000041c) + +#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA) +#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA) +#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA) +#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA) +#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA) +#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA) +#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA) +#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA) + +#define HW_PINCTRL_DRIVE18 (0x00000420) +#define HW_PINCTRL_DRIVE18_SET (0x00000424) +#define HW_PINCTRL_DRIVE18_CLR (0x00000428) +#define HW_PINCTRL_DRIVE18_TOG (0x0000042c) + +#define BP_PINCTRL_DRIVE18_RSRVD3 20 +#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000 +#define BF_PINCTRL_DRIVE18_RSRVD3(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3) +#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA) +#define BP_PINCTRL_DRIVE18_RSRVD1 4 +#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0 +#define BF_PINCTRL_DRIVE18_RSRVD1(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1) +#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA) + +#define HW_PINCTRL_DRIVE19 (0x00000430) +#define HW_PINCTRL_DRIVE19_SET (0x00000434) +#define HW_PINCTRL_DRIVE19_CLR (0x00000438) +#define HW_PINCTRL_DRIVE19_TOG (0x0000043c) + +#define BP_PINCTRL_DRIVE19_RSRVD0 0 +#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v) + +#define HW_PINCTRL_PULL0 (0x00000600) +#define HW_PINCTRL_PULL0_SET (0x00000604) +#define HW_PINCTRL_PULL0_CLR (0x00000608) +#define HW_PINCTRL_PULL0_TOG (0x0000060c) + +#define BP_PINCTRL_PULL0_RSRVD1 29 +#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000 +#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000 +#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000 +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000 +#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000 +#define BP_PINCTRL_PULL0_RSRVD0 8 +#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000610) +#define HW_PINCTRL_PULL1_SET (0x00000614) +#define HW_PINCTRL_PULL1_CLR (0x00000618) +#define HW_PINCTRL_PULL1_TOG (0x0000061c) + +#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000 +#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000 +#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000 +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 +#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000 +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000 +#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000 +#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000 +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000 +#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000 +#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000 +#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000 +#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000 +#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000 +#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800 +#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400 +#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200 +#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100 +#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080 +#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040 +#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020 +#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010 +#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008 +#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004 +#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002 +#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001 + +#define HW_PINCTRL_PULL2 (0x00000620) +#define HW_PINCTRL_PULL2_SET (0x00000624) +#define HW_PINCTRL_PULL2_CLR (0x00000628) +#define HW_PINCTRL_PULL2_TOG (0x0000062c) + +#define BP_PINCTRL_PULL2_RSRVD2 28 +#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000 +#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000 +#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000 +#define BP_PINCTRL_PULL2_RSRVD1 22 +#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000 +#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000 +#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000 +#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000 +#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000 +#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000 +#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000 +#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000 +#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000 +#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000 +#define BM_PINCTRL_PULL2_RSRVD0 0x00000800 +#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400 +#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200 +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080 +#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040 +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000630) +#define HW_PINCTRL_PULL3_SET (0x00000634) +#define HW_PINCTRL_PULL3_CLR (0x00000638) +#define HW_PINCTRL_PULL3_TOG (0x0000063c) + +#define BM_PINCTRL_PULL3_RSRVD1 0x80000000 +#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000 +#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000 +#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000 +#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000 +#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000 +#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000 +#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000 +#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000 +#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000 +#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000 +#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000 +#define BM_PINCTRL_PULL3_RSRVD0 0x00080000 +#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000 +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_PULL4 (0x00000640) +#define HW_PINCTRL_PULL4_SET (0x00000644) +#define HW_PINCTRL_PULL4_CLR (0x00000648) +#define HW_PINCTRL_PULL4_TOG (0x0000064c) + +#define BP_PINCTRL_PULL4_RSRVD1 21 +#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PULL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1) +#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000 +#define BP_PINCTRL_PULL4_RSRVD0 17 +#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000 +#define BF_PINCTRL_PULL4_RSRVD0(v) \ + (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0) +#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000 +#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000 +#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000 +#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000 +#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000 +#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800 +#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400 +#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200 +#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100 +#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080 +#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040 +#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020 +#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010 +#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008 +#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004 +#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002 +#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001 + +#define HW_PINCTRL_PULL5 (0x00000650) +#define HW_PINCTRL_PULL5_SET (0x00000654) +#define HW_PINCTRL_PULL5_CLR (0x00000658) +#define HW_PINCTRL_PULL5_TOG (0x0000065c) + +#define BP_PINCTRL_PULL5_RSRVD1 27 +#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000 +#define BF_PINCTRL_PULL5_RSRVD1(v) \ + (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1) +#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000 +#define BP_PINCTRL_PULL5_RSRVD0 24 +#define BM_PINCTRL_PULL5_RSRVD0 0x03000000 +#define BF_PINCTRL_PULL5_RSRVD0(v) \ + (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0) +#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000 +#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000 +#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000 +#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000 +#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000 +#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000 +#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000 +#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000 +#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000 +#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000 +#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000 +#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000 +#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800 +#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400 +#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200 +#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100 +#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080 +#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040 +#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020 +#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010 +#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008 +#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004 +#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002 +#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001 + +#define HW_PINCTRL_PULL6 (0x00000660) +#define HW_PINCTRL_PULL6_SET (0x00000664) +#define HW_PINCTRL_PULL6_CLR (0x00000668) +#define HW_PINCTRL_PULL6_TOG (0x0000066c) + +#define BP_PINCTRL_PULL6_RSRVD1 25 +#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000 +#define BF_PINCTRL_PULL6_RSRVD1(v) \ + (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1) +#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000 +#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000 +#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000 +#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000 +#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000 +#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000 +#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000 +#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000 +#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000 +#define BM_PINCTRL_PULL6_RSRVD0 0x00008000 +#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000 +#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000 +#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000 +#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800 +#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400 +#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200 +#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100 +#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080 +#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040 +#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020 +#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010 +#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008 +#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004 +#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002 +#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000700) +#define HW_PINCTRL_DOUT0_SET (0x00000704) +#define HW_PINCTRL_DOUT0_CLR (0x00000708) +#define HW_PINCTRL_DOUT0_TOG (0x0000070c) + +#define BP_PINCTRL_DOUT0_RSRVD1 29 +#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOUT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1) +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT0_DOUT) + +#define HW_PINCTRL_DOUT1 (0x00000710) +#define HW_PINCTRL_DOUT1_SET (0x00000714) +#define HW_PINCTRL_DOUT1_CLR (0x00000718) +#define HW_PINCTRL_DOUT1_TOG (0x0000071c) + +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) (v) + +#define HW_PINCTRL_DOUT2 (0x00000720) +#define HW_PINCTRL_DOUT2_SET (0x00000724) +#define HW_PINCTRL_DOUT2_CLR (0x00000728) +#define HW_PINCTRL_DOUT2_TOG (0x0000072c) + +#define BP_PINCTRL_DOUT2_RSRVD1 28 +#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOUT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1) +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT2_DOUT) + +#define HW_PINCTRL_DOUT3 (0x00000730) +#define HW_PINCTRL_DOUT3_SET (0x00000734) +#define HW_PINCTRL_DOUT3_CLR (0x00000738) +#define HW_PINCTRL_DOUT3_TOG (0x0000073c) + +#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT3_DOUT 0 +#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT3_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT3_DOUT) + +#define HW_PINCTRL_DOUT4 (0x00000740) +#define HW_PINCTRL_DOUT4_SET (0x00000744) +#define HW_PINCTRL_DOUT4_CLR (0x00000748) +#define HW_PINCTRL_DOUT4_TOG (0x0000074c) + +#define BP_PINCTRL_DOUT4_RSRVD1 21 +#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOUT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1) +#define BP_PINCTRL_DOUT4_DOUT 0 +#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF +#define BF_PINCTRL_DOUT4_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT4_DOUT) + +#define HW_PINCTRL_DIN0 (0x00000900) +#define HW_PINCTRL_DIN0_SET (0x00000904) +#define HW_PINCTRL_DIN0_CLR (0x00000908) +#define HW_PINCTRL_DIN0_TOG (0x0000090c) + +#define BP_PINCTRL_DIN0_RSRVD1 29 +#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DIN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1) +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN0_DIN) + +#define HW_PINCTRL_DIN1 (0x00000910) +#define HW_PINCTRL_DIN1_SET (0x00000914) +#define HW_PINCTRL_DIN1_CLR (0x00000918) +#define HW_PINCTRL_DIN1_TOG (0x0000091c) + +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) (v) + +#define HW_PINCTRL_DIN2 (0x00000920) +#define HW_PINCTRL_DIN2_SET (0x00000924) +#define HW_PINCTRL_DIN2_CLR (0x00000928) +#define HW_PINCTRL_DIN2_TOG (0x0000092c) + +#define BP_PINCTRL_DIN2_RSRVD1 28 +#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DIN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1) +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN2_DIN) + +#define HW_PINCTRL_DIN3 (0x00000930) +#define HW_PINCTRL_DIN3_SET (0x00000934) +#define HW_PINCTRL_DIN3_CLR (0x00000938) +#define HW_PINCTRL_DIN3_TOG (0x0000093c) + +#define BM_PINCTRL_DIN3_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN3_DIN 0 +#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN3_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN3_DIN) + +#define HW_PINCTRL_DIN4 (0x00000940) +#define HW_PINCTRL_DIN4_SET (0x00000944) +#define HW_PINCTRL_DIN4_CLR (0x00000948) +#define HW_PINCTRL_DIN4_TOG (0x0000094c) + +#define BP_PINCTRL_DIN4_RSRVD1 21 +#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DIN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1) +#define BP_PINCTRL_DIN4_DIN 0 +#define BM_PINCTRL_DIN4_DIN 0x001FFFFF +#define BF_PINCTRL_DIN4_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN4_DIN) + +#define HW_PINCTRL_DOE0 (0x00000b00) +#define HW_PINCTRL_DOE0_SET (0x00000b04) +#define HW_PINCTRL_DOE0_CLR (0x00000b08) +#define HW_PINCTRL_DOE0_TOG (0x00000b0c) + +#define BP_PINCTRL_DOE0_RSRVD1 29 +#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOE0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1) +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE0_DOE) + +#define HW_PINCTRL_DOE1 (0x00000b10) +#define HW_PINCTRL_DOE1_SET (0x00000b14) +#define HW_PINCTRL_DOE1_CLR (0x00000b18) +#define HW_PINCTRL_DOE1_TOG (0x00000b1c) + +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) (v) + +#define HW_PINCTRL_DOE2 (0x00000b20) +#define HW_PINCTRL_DOE2_SET (0x00000b24) +#define HW_PINCTRL_DOE2_CLR (0x00000b28) +#define HW_PINCTRL_DOE2_TOG (0x00000b2c) + +#define BP_PINCTRL_DOE2_RSRVD1 28 +#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOE2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1) +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE2_DOE) + +#define HW_PINCTRL_DOE3 (0x00000b30) +#define HW_PINCTRL_DOE3_SET (0x00000b34) +#define HW_PINCTRL_DOE3_CLR (0x00000b38) +#define HW_PINCTRL_DOE3_TOG (0x00000b3c) + +#define BM_PINCTRL_DOE3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE3_DOE 0 +#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE3_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE3_DOE) + +#define HW_PINCTRL_DOE4 (0x00000b40) +#define HW_PINCTRL_DOE4_SET (0x00000b44) +#define HW_PINCTRL_DOE4_CLR (0x00000b48) +#define HW_PINCTRL_DOE4_TOG (0x00000b4c) + +#define BP_PINCTRL_DOE4_RSRVD1 21 +#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOE4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1) +#define BP_PINCTRL_DOE4_DOE 0 +#define BM_PINCTRL_DOE4_DOE 0x001FFFFF +#define BF_PINCTRL_DOE4_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE4_DOE) + +#define HW_PINCTRL_PIN2IRQ0 (0x00001000) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00001004) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00001008) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000100c) + +#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29 +#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1) +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ1 (0x00001010) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00001014) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00001018) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000101c) + +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ2 (0x00001020) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00001024) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00001028) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000102c) + +#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28 +#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000 +#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1) +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ3 (0x00001030) +#define HW_PINCTRL_PIN2IRQ3_SET (0x00001034) +#define HW_PINCTRL_PIN2IRQ3_CLR (0x00001038) +#define HW_PINCTRL_PIN2IRQ3_TOG (0x0000103c) + +#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ4 (0x00001040) +#define HW_PINCTRL_PIN2IRQ4_SET (0x00001044) +#define HW_PINCTRL_PIN2IRQ4_CLR (0x00001048) +#define HW_PINCTRL_PIN2IRQ4_TOG (0x0000104c) + +#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21 +#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1) +#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF +#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ) + +#define HW_PINCTRL_IRQEN0 (0x00001100) +#define HW_PINCTRL_IRQEN0_SET (0x00001104) +#define HW_PINCTRL_IRQEN0_CLR (0x00001108) +#define HW_PINCTRL_IRQEN0_TOG (0x0000110c) + +#define BP_PINCTRL_IRQEN0_RSRVD1 29 +#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQEN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1) +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN) + +#define HW_PINCTRL_IRQEN1 (0x00001110) +#define HW_PINCTRL_IRQEN1_SET (0x00001114) +#define HW_PINCTRL_IRQEN1_CLR (0x00001118) +#define HW_PINCTRL_IRQEN1_TOG (0x0000111c) + +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN2 (0x00001120) +#define HW_PINCTRL_IRQEN2_SET (0x00001124) +#define HW_PINCTRL_IRQEN2_CLR (0x00001128) +#define HW_PINCTRL_IRQEN2_TOG (0x0000112c) + +#define BP_PINCTRL_IRQEN2_RSRVD1 28 +#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQEN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1) +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN) + +#define HW_PINCTRL_IRQEN3 (0x00001130) +#define HW_PINCTRL_IRQEN3_SET (0x00001134) +#define HW_PINCTRL_IRQEN3_CLR (0x00001138) +#define HW_PINCTRL_IRQEN3_TOG (0x0000113c) + +#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN3_IRQEN 0 +#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN3_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN) + +#define HW_PINCTRL_IRQEN4 (0x00001140) +#define HW_PINCTRL_IRQEN4_SET (0x00001144) +#define HW_PINCTRL_IRQEN4_CLR (0x00001148) +#define HW_PINCTRL_IRQEN4_TOG (0x0000114c) + +#define BP_PINCTRL_IRQEN4_RSRVD1 21 +#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQEN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1) +#define BP_PINCTRL_IRQEN4_IRQEN 0 +#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF +#define BF_PINCTRL_IRQEN4_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN) + +#define HW_PINCTRL_IRQLEVEL0 (0x00001200) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00001204) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00001208) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x0000120c) + +#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29 +#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1) +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL1 (0x00001210) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00001214) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00001218) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x0000121c) + +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL2 (0x00001220) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00001224) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00001228) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x0000122c) + +#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28 +#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1) +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL3 (0x00001230) +#define HW_PINCTRL_IRQLEVEL3_SET (0x00001234) +#define HW_PINCTRL_IRQLEVEL3_CLR (0x00001238) +#define HW_PINCTRL_IRQLEVEL3_TOG (0x0000123c) + +#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL4 (0x00001240) +#define HW_PINCTRL_IRQLEVEL4_SET (0x00001244) +#define HW_PINCTRL_IRQLEVEL4_CLR (0x00001248) +#define HW_PINCTRL_IRQLEVEL4_TOG (0x0000124c) + +#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21 +#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1) +#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF +#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL) + +#define HW_PINCTRL_IRQPOL0 (0x00001300) +#define HW_PINCTRL_IRQPOL0_SET (0x00001304) +#define HW_PINCTRL_IRQPOL0_CLR (0x00001308) +#define HW_PINCTRL_IRQPOL0_TOG (0x0000130c) + +#define BP_PINCTRL_IRQPOL0_RSRVD1 29 +#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1) +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL) + +#define HW_PINCTRL_IRQPOL1 (0x00001310) +#define HW_PINCTRL_IRQPOL1_SET (0x00001314) +#define HW_PINCTRL_IRQPOL1_CLR (0x00001318) +#define HW_PINCTRL_IRQPOL1_TOG (0x0000131c) + +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL2 (0x00001320) +#define HW_PINCTRL_IRQPOL2_SET (0x00001324) +#define HW_PINCTRL_IRQPOL2_CLR (0x00001328) +#define HW_PINCTRL_IRQPOL2_TOG (0x0000132c) + +#define BP_PINCTRL_IRQPOL2_RSRVD1 28 +#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1) +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL) + +#define HW_PINCTRL_IRQPOL3 (0x00001330) +#define HW_PINCTRL_IRQPOL3_SET (0x00001334) +#define HW_PINCTRL_IRQPOL3_CLR (0x00001338) +#define HW_PINCTRL_IRQPOL3_TOG (0x0000133c) + +#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL3_IRQPOL 0 +#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL) + +#define HW_PINCTRL_IRQPOL4 (0x00001340) +#define HW_PINCTRL_IRQPOL4_SET (0x00001344) +#define HW_PINCTRL_IRQPOL4_CLR (0x00001348) +#define HW_PINCTRL_IRQPOL4_TOG (0x0000134c) + +#define BP_PINCTRL_IRQPOL4_RSRVD1 21 +#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1) +#define BP_PINCTRL_IRQPOL4_IRQPOL 0 +#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF +#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL) + +#define HW_PINCTRL_IRQSTAT0 (0x00001400) +#define HW_PINCTRL_IRQSTAT0_SET (0x00001404) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00001408) +#define HW_PINCTRL_IRQSTAT0_TOG (0x0000140c) + +#define BP_PINCTRL_IRQSTAT0_RSRVD1 29 +#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1) +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT1 (0x00001410) +#define HW_PINCTRL_IRQSTAT1_SET (0x00001414) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00001418) +#define HW_PINCTRL_IRQSTAT1_TOG (0x0000141c) + +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT2 (0x00001420) +#define HW_PINCTRL_IRQSTAT2_SET (0x00001424) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00001428) +#define HW_PINCTRL_IRQSTAT2_TOG (0x0000142c) + +#define BP_PINCTRL_IRQSTAT2_RSRVD1 28 +#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1) +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT3 (0x00001430) +#define HW_PINCTRL_IRQSTAT3_SET (0x00001434) +#define HW_PINCTRL_IRQSTAT3_CLR (0x00001438) +#define HW_PINCTRL_IRQSTAT3_TOG (0x0000143c) + +#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT4 (0x00001440) +#define HW_PINCTRL_IRQSTAT4_SET (0x00001444) +#define HW_PINCTRL_IRQSTAT4_CLR (0x00001448) +#define HW_PINCTRL_IRQSTAT4_TOG (0x0000144c) + +#define BP_PINCTRL_IRQSTAT4_RSRVD1 21 +#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1) +#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF +#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT) + +#define HW_PINCTRL_EMI_ODT_CTRL (0x00001a40) +#define HW_PINCTRL_EMI_ODT_CTRL_SET (0x00001a44) +#define HW_PINCTRL_EMI_ODT_CTRL_CLR (0x00001a48) +#define HW_PINCTRL_EMI_ODT_CTRL_TOG (0x00001a4c) + +#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28 +#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000 +#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \ + (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \ + (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \ + (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \ + (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \ + (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \ + (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \ + (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \ + (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \ + (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \ + (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \ + (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \ + (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \ + (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \ + (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD) + +#define HW_PINCTRL_EMI_DS_CTRL (0x00001b80) +#define HW_PINCTRL_EMI_DS_CTRL_SET (0x00001b84) +#define HW_PINCTRL_EMI_DS_CTRL_CLR (0x00001b88) +#define HW_PINCTRL_EMI_DS_CTRL_TOG (0x00001b8c) + +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \ + (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16 +#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000 +#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \ + (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11 +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0) +#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12 +#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000 +#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \ + (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA) +#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10 +#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00 +#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \ + (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA) +#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8 +#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300 +#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \ + (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \ + (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \ + (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C +#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \ + (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \ + (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-mx28/serial.c b/arch/arm/mach-mx28/serial.c new file mode 100644 index 000000000000..a7297d1f62f6 --- /dev/null +++ b/arch/arm/mach-mx28/serial.c @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is distributed in the hope that it will be useful, + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/dma.h> +#include "device.h" + +#if defined(CONFIG_SERIAL_MXS_AUART) || \ + defined(CONFIG_SERIAL_MXS_AUART_MODULE) + +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE +static struct resource auart0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART0_PHYS_ADDR, + .end = AUART0_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0, + .end = IRQ_AUART0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_RX_DMA, + .end = IRQ_AUART0_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_TX_DMA, + .end = IRQ_AUART0_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart0_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART0_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE +static struct resource auart1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART1_PHYS_ADDR, + .end = AUART1_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1, + .end = IRQ_AUART1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_RX_DMA, + .end = IRQ_AUART1_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_TX_DMA, + .end = IRQ_AUART1_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart1_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART1_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE +static struct resource auart2_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART2_PHYS_ADDR, + .end = AUART2_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2, + .end = IRQ_AUART2, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_RX_DMA, + .end = IRQ_AUART2_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_TX_DMA, + .end = IRQ_AUART2_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart2_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART2_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE +static struct resource auart3_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART3_PHYS_ADDR, + .end = AUART3_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3, + .end = IRQ_AUART3, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_RX_DMA, + .end = IRQ_AUART3_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_TX_DMA, + .end = IRQ_AUART3_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart3_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART3_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE +static struct resource auart4_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART4_PHYS_ADDR, + .end = AUART4_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4, + .end = IRQ_AUART4, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_RX_DMA, + .end = IRQ_AUART4_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_TX_DMA, + .end = IRQ_AUART4_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart4_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART4_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +void __init mx28_init_auart(void) +{ + int i; + struct mxs_dev_lookup *plookup; + struct platform_device *pdev; + + plookup = mxs_get_devices("mxs-auart"); + if (plookup == NULL || IS_ERR(plookup)) + return; + for (i = 0; i < plookup->size; i++) { + pdev = plookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + case 0: + pdev->resource = auart0_resource; + pdev->num_resources = ARRAY_SIZE(auart0_resource); + pdev->dev.platform_data = &mxs_auart0_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + case 1: + pdev->resource = auart1_resource; + pdev->num_resources = ARRAY_SIZE(auart1_resource); + pdev->dev.platform_data = &mxs_auart1_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + case 2: + pdev->resource = auart2_resource; + pdev->num_resources = ARRAY_SIZE(auart2_resource); + pdev->dev.platform_data = &mxs_auart2_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + case 3: + pdev->resource = auart3_resource; + pdev->num_resources = ARRAY_SIZE(auart3_resource); + pdev->dev.platform_data = &mxs_auart3_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE + case 4: + pdev->resource = auart4_resource; + pdev->num_resources = ARRAY_SIZE(auart4_resource); + pdev->dev.platform_data = &mxs_auart4_platdata; + break; +#endif + default: + break; + } + mxs_add_device(pdev, 3); + } +} +#else +void __init mx28_init_auart(void) +{ +} +#endif diff --git a/arch/arm/mach-mx28/sleep.S b/arch/arm/mach-mx28/sleep.S new file mode 100644 index 000000000000..6c62bae310eb --- /dev/null +++ b/arch/arm/mach-mx28/sleep.S @@ -0,0 +1,698 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> +#include <asm/system.h> +#include <asm/pgtable-hwdef.h> +#include <mach/hardware.h> +#include <mach/regs-power.h> +#include <mach/regs-rtc.h> +#include "regs-pinctrl.h" +#include "regs-clkctrl.h" +#include "regs-dram.h" +#include "sleep.h" + +#define BM_DRAM_CTL17_SREFRESH 0x00000001 +#define HW_CLKCTRL_CPU_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_CPU) +#define HW_POWER_MINPWR_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) +#define HW_POWER_RESET_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_RESET) + +#define HW_DRAM_CTL17_ADDR \ + (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL17) +#define HW_DRAM_CTL22_ADDR \ + (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL22) + +#define HW_RTC_PERSISTENT0_ADDR \ + (MX28_SOC_IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT0) +#define HW_CLKCTRL_EMI_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_EMI) +#define HW_CLKCTRL_PLL0CTRL0_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_PLL0CTRL0) +#define HW_POWER_VDDIOCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDIOCTRL) +#define HW_POWER_VDDDCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDDCTRL) +#define HW_POWER_VDDACTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDACTRL) +#define HW_PINCTRL_EMI_DS_CTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(PINCTRL_PHYS_ADDR) + HW_PINCTRL_EMI_DS_CTRL) + +#define HW_POWER_5VCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_5VCTRL) +#define HW_POWER_LOOPCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_LOOPCTRL) +#define HW_POWER_STS_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_STS) +#define HW_POWER_MINPWR_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) + +#define PHYS_RAM_START 0x40000000 + +#define LOWER_VDDIO 5 +#define LOWER_VDDA 9 +#define LOWER_VDDD 12 + +#define VDDIOCTRL_BACKUP 0 +#define VDDACTRL_BACKUP 1 +#define VDDDCTRL_BACKUP 2 +#define POWER_LOOPCTRL_BACKUP 3 +#define POWER_MINPWR_BACKUP 4 + +.macro PM_BITS_SET, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BITS_CLR, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BACKUP_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 +.endm + +.macro PM_WRITE_REG_MASK, addr, bitmask, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_AND_BACKUP_REG, addr, bitmask, val, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_RESTORE_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, __mx28_temp_stack + \num * 4 + str r1, [r0] +.endm + + +.global cpu_arm926_switch_mm + + .text + +.align 8 +ENTRY(mx28_cpu_standby) + @ save registers on stack + stmfd sp!, {r0 - r9, lr} + + adr r9, __mx28_temp_stack + + @ clean cache + ldr r1, __mx28_flush_cache_addr + mov lr, pc + mov pc, r1 + @ put DRAM into self refresh + mov r0, #(HW_DRAM_CTL22_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0xFF000000) + ldr r1,[r0] + and r1, r1, #(~BM_DRAM_CTL22_LOWPOWER_CONTROL) + orr r1, r1, #(BF_DRAM_CTL22_LOWPOWER_CONTROL(2)) + str r1, [r0] + + @ wait for it to actually happen + mov r0, #24 << 12 +11: sub r0, r0, #1 + cmp r0, #0 + bne 11b + + @ gate clk + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(BM_CLKCTRL_EMI_CLKGATE) + str r1, [r0] + +// PM_SET_AND_BACKUP_REG HW_PINCTRL_EMI_DS_CTRL_ADDR,\ +// BM_PINCTRL_EMI_DS_CTRL_DDR_MODE,\ +// BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1), 4 + + mov r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0xFF000000) + ldr r1, [r0] + and r1, r1, #(~BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) + orr r1, r1, #(BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1)) + str r1, [r0] + + mov r2, #(HW_POWER_STS_ADDR & 0x000000FF) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x0000FF00) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x00FF0000) + orr r2, r2, #(HW_POWER_STS_ADDR & 0xFF000000) + // vddio + PM_SET_AND_BACKUP_REG HW_POWER_VDDIOCTRL_ADDR,\ + BM_POWER_VDDIOCTRL_TRG, LOWER_VDDIO, VDDIOCTRL_BACKUP + +7: + mov r0, #24 << 10 +1: sub r0, r0, #1 + cmp r0, #0 + bne 1b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 7b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDACTRL_ADDR,\ + BM_POWER_VDDACTRL_TRG, LOWER_VDDA, VDDACTRL_BACKUP +8: + mov r0, #24 << 10 +2: sub r0, r0, #1 + cmp r0, #0 + bne 2b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 8b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDDCTRL_ADDR,\ + BM_POWER_VDDDCTRL_TRG, LOWER_VDDD, VDDDCTRL_BACKUP +9: + mov r0, #24 << 10 +3: sub r0, r0, #1 + cmp r0, #0 + bne 3b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 9b + + @ wait for DC OK + mov r0, #(HW_POWER_STS_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_STS_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_STS_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_STS_ADDR & 0xFF000000) +4: ldr r1,[r0] + and r1,r1,#(BM_POWER_STS_DC_OK) + cmp r1,#(BM_POWER_STS_DC_OK) + bne 4b + + PM_BACKUP_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP + PM_BACKUP_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP + + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_RCSCALE + PM_WRITE_REG_MASK HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_DC_R,\ + (2<<BP_POWER_LOOPCTRL_DC_R) + + // half fets + PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_HALF_FETS + + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_CM_HYST_THRESH + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_CM_HYST + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_DF_HYST + + // enable PFM + PM_BITS_SET HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_HYST_SIGN + PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_EN_DC_PFM + + + PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_LESSANA_I + + PM_BITS_SET HW_POWER_5VCTRL_ADDR, BM_POWER_5VCTRL_ILIMIT_EQ_ZERO + //Gated PLL0 + PM_BITS_CLR HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER + + @ do enter standby + mov r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0xFF000000) + mov r1, #(1<<12) + str r1, [r0, #4] + mov r2, #0 + mcr p15, 0, r2, c7, c0, 4 + nop + + @ sleeping now... + + @ remove INTERRUPT_WAIT bit + str r1, [r0, #8] + nop + nop + nop + + mov r2, #(HW_POWER_STS_ADDR & 0x000000FF) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x0000FF00) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x00FF0000) + orr r2, r2, #(HW_POWER_STS_ADDR & 0xFF000000) + + PM_BITS_SET HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER + + PM_SET_RESTORE_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP + + PM_SET_RESTORE_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP + + PM_BITS_CLR HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_LESSANA_I + + PM_BITS_CLR HW_POWER_5VCTRL_ADDR, BM_POWER_5VCTRL_ILIMIT_EQ_ZERO + // vddio + PM_SET_RESTORE_REG HW_POWER_VDDIOCTRL_ADDR, VDDIOCTRL_BACKUP +77: + mov r0, #24 << 10 +10: sub r0, r0, #1 + cmp r0, #0 + bne 10b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 77b + + PM_SET_RESTORE_REG HW_POWER_VDDACTRL_ADDR, VDDACTRL_BACKUP +88: + mov r0, #24 << 10 +20: sub r0, r0, #1 + cmp r0, #0 + bne 20b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 88b + + PM_SET_RESTORE_REG HW_POWER_VDDDCTRL_ADDR, VDDDCTRL_BACKUP +99: + mov r0, #24 << 10 +30: sub r0, r0, #1 + cmp r0, #0 + bne 30b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 99b + + mov r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0xFF000000) + ldr r1, [r0] + and r1, r1, #(~BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) + orr r1, r1, #(BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(3)) + str r1, [r0] + + @ ungate clk + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(BM_CLKCTRL_EMI_CLKGATE) + str r1, [r0] + +// PM_SET_RESTORE_REG HW_PINCTRL_EMI_DS_CTRL_ADDR, 4 + @ restore normal DRAM mode + mov r0, #(HW_DRAM_CTL22_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(BF_DRAM_CTL22_LOWPOWER_CONTROL(2)) + str r1, [r0] + @ wait for it to actually happen + mov r0, #24 << 12 +12: sub r0, r0, #1 + cmp r0, #0 + bne 12b + + nop + nop + nop + + @ restore regs and return + ldmfd sp!, {r0 - r9, pc} + + .space 0x100 +__mx28_temp_stack: + .space 128 + +#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING +#include "emi.inc" +#endif + +__mx28_flush_cache_addr: + .word arm926_flush_kern_cache_all + +ENTRY(mx28_standby_alloc_sz) + .word . - mx28_cpu_standby + +ENTRY(mx28_cpu_suspend) + @ save registers on stack + stmfd sp!, {r1 - r12, lr} + + @ save context + mov r0, #0xd3 @ SVC, Interrupts disabled + msr cpsr, r0 + mov r1, #0xC0000000 + ldr r1, [r1] + mrc p15, 0, r0, c1, c0, 0 + str r0, [r1, #MMUCTL_OFFS] + mrc p15, 0, r0, c15, c1, 0 + str r0, [r1, #MMUCPACCESS_OFS] + mrc p15, 0, r0, c2, c0, 0 + str r0, [r1, #MMUTTB_OFFS] + mrc p15, 0, r0, c3, c0, 0 + str r0, [r1, #MMUDOMAIN_OFFS] + mrc p15, 0, r0, c13, c0, 0 + str r0, [r1, #MMUPID_OFFS] + + str sp, [r1, #SVC_SP_OFFS] + mrs r0, spsr + str r0, [r1, #SVC_SPSR_OFFS] + + add r2, r1, #FIQ_SPSR_OFFS + mov r0, #0xd1 @ FIQ, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, r8-r12, sp, lr} + + add r2, r1, #ABT_SPSR_OFFS + mov r0, #0xd7 @ ABT, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #IRQ_SPSR_OFFS + mov r0, #0xd2 @ IRQ, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #UND_SPSR_OFFS + mov r0, #0xdb @ UND, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #SYS_SP_OFFS + mov r0, #0xdf @ SYS, Interrupts disabled + msr cpsr, r0 + stmia r2!, {sp, lr} + + add r2, r1, #SVC_R8_OFFS + mov r0, #0xd3 @ Back to SVC, Interrupts disabled + msr cpsr, r0 + + @ save entry point + sub r1, r1, #(0xC0000000 - PHYS_RAM_START) + mov r0, #0xC0000000 + str r1, [r0] + ldr r1, __mx28_resume_point + sub r1, r1, #(0xC0000000 - PHYS_RAM_START) + str r1, [r0, #4] + mov r0, #0 + + @ clean cache + ldr r1, __mx28_flush_cache_addr2 + mov lr, pc + mov pc, r1 + + @ enable internal xtal + mov r2, #(HW_POWER_MINPWR_ADDR & 0x000000FF) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x0000FF00) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x00FF0000) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0xFF000000) + ldr r1, [r2] + orr r1, r1, #(1<<9) + str r1, [r2] + orr r1, r1, #(1<<8) + str r1, [r2] + + @ enable RTC/RAM clocks + mov r0, #(HW_RTC_PERSISTENT0_ADDR & 0x000000FF) + orr r0, r0, #(HW_RTC_PERSISTENT0_ADDR & 0x0000FF00) + orr r0, r0, #(HW_RTC_PERSISTENT0_ADDR & 0x00FF0000) + orr r0, r0, #(HW_RTC_PERSISTENT0_ADDR & 0xFF000000) + mov r1, #((1<<4)|(1<<5)|1) + str r1, [r0, #4] + + @ put DRAM into self refresh + mov r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(BM_DRAM_CTL17_SREFRESH) + str r1, [r0] + + @ wait for it to actually happen + nop + nop + nop + nop + nop + nop + + @ power off RAM + mov r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(1<<24) + str r1, [r0] + nop + nop + nop + nop + + @ do enter sleep + mov r0, #(HW_POWER_RESET_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0xFF000000) + mov r1, #0xFF000000 + orr r1, r1, #0x00FF0000 + str r1, [r0, #8] + mov r1, #0x3E000000 + orr r1, r1, #0x00770000 + str r1, [r0, #4] + mov r1, #2 + str r1, [r0, #8] + mov r1, #1 + str r1, [r0, #4] + nop + nop + nop + nop + nop + nop + + @ sleeping now... + +__restore_context: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer + mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs + mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache + nop + nop + + mov r0, #0xd3 + msr cpsr, r0 + + bl __create_temp_page_tables + mov r3, r4 + + mov r1, #PHYS_RAM_START + ldr r1, [r1] + ldr r2, [r1, #MMUDOMAIN_OFFS] + ldr r4, [r1, #MMUCPACCESS_OFS] + ldr r5, [r1, #MMUPID_OFFS] + ldr r6, =__resume_after_mmu + ldr r7, [r1, #MMUCTL_OFFS] + ldr r8, [r1, #MMUTTB_OFFS] + add r1, r1, #(0xC0000000 - PHYS_RAM_START) + mov r0, #0 +@ mcr p15, 0, r4, c15, c1, 0 @ cpaccess + mcr p15, 0, r5, c13, c0, 0 @ pid + mcr p15, 0, r2, c3, c0, 0 @ domain + mcr p15, 0, r3, c2, c0, 0 @ ttb + b 1f + .align 5 +1: mov r0, r0 + mcr p15, 0, r7, c1, c0, 0 @ mmuctl + nop + mrc p15, 0, r0, c3, c0, 0 @ read id + mov r0, r0 + mov r0, r0 + sub pc, r6, r5, lsr #32 + nop + nop + nop +__resume_after_mmu: + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs + mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache + + mov r0, r8 + bl cpu_arm926_switch_mm + + mov r0, #0xd1 @FIQ, Interrupts disabled + ldr r2, [r1, #FIQ_SPSR_OFFS] + add r3, r1, #FIQ_R8_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {r8-r12, sp, lr} + + mov r0, #0xd7 @ABT, Interrupts disabled + ldr r2, [r1, #ABT_SPSR_OFFS] + add r3, r1, #ABT_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xd2 @IRQ, Interrupts disabled + ldr r2, [r1, #IRQ_SPSR_OFFS] + add r3, r1, #IRQ_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xdb @UND, Interrupts disabled + ldr r2, [r1, #UND_SPSR_OFFS] + add r3, r1, #UND_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xdf @SYS, Interrupts disabled + add r3, r1, #SYS_SP_OFFS + msr cpsr, r0 + ldmia r3!, {sp, lr} + + mov r0, #0xd3 @SVC, interrupts disabled + ldr r2, [r1, #SVC_SPSR_OFFS] + ldr r3, [r1, #SVC_SP_OFFS] + msr cpsr, r0 + msr spsr, r2 + mov sp, r3 + +#if 0 + @ select CPU bypass, will be cleared afterwards + ldr r0, =HW_CLKCTRL_CLKSEQ_ADDR + ldr r2, =HW_CLKCTRL_HBUS_ADDR + ldr r4, =HW_CLKCTRL_CPU_ADDR + mov r1, #(1<<7) + ldr r3, [r2] + bic r3, r3, #BM_CLKCTRL_HBUS_DIV + orr r3, r3, #1 + ldr r5, [r4] + bic r5, r5, #BM_CLKCTRL_CPU_DIV_CPU + orr r5, r5, #1 + str r1, [r0, #4] + str r3, [r2] + str r5, [r4] +#endif + @ restore regs and return + ldmfd sp!, {r1 - r12, lr} + mov pc, lr + +__mx28_flush_cache_addr2: + .word arm926_flush_kern_cache_all +__mx28_resume_point: + .word __restore_context +ENTRY(mx28_s2ram_alloc_sz) + .word . - mx28_cpu_suspend + +__create_temp_page_tables: + ldr r4, =(__temp_ttb - 0xC0000000 + PHYS_RAM_START) + + /* + * Clear the 16K level 1 swapper page table + */ + mov r0, r4 + mov r3, #0 + add r6, r0, #0x4000 +1: str r3, [r0], #4 + str r3, [r0], #4 + str r3, [r0], #4 + str r3, [r0], #4 + teq r0, r6 + bne 1b + + /* + * Create identity mapping for the area close to where we are to + * cater for the MMU enable. + */ + mov r6, pc, lsr #20 @ kind of where we are + ldr r7, =\ + (PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE\ + | PMD_BIT4 | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ) + + orr r3, r7, r6, lsl #20 @ flags + kernel base + str r3, [r4, r6, lsl #2] @ identity mapping + + mov r6, r6, lsl #20 + add r6, r6, #(0xC0000000-PHYS_RAM_START) + str r3, [r4, r6, lsr #18] + + mov pc, lr + .ltorg + + .section ".sdata", "a" + .align 14 +__temp_ttb: + .space 0x8000 diff --git a/arch/arm/mach-mx28/sleep.h b/arch/arm/mach-mx28/sleep.h new file mode 100644 index 000000000000..678d5527a3d8 --- /dev/null +++ b/arch/arm/mach-mx28/sleep.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#ifndef __PM_H__ +#define __PM_H__ + +#include "regs-clkctrl.h" + +#define MMUTTB1_MASK 0x00003FE0 +#define MMUTTBC_MASK 0xFFFFFFFC + +#define LINK_OFFS 0x08 +#define MMUCTL_OFFS 0x0C +#define MMUAUXCTL_OFFS 0x10 +#define MMUCPACCESS_OFS 0x14 +#define MMUTTB_OFFS 0x18 +#define MMUPID_OFFS 0x1C +#define MMUDOMAIN_OFFS 0x20 +#define SVC_R8_OFFS 0x2C +#define SVC_SP_OFFS 0x40 +#define SVC_SPSR_OFFS 0x44 +#define FIQ_SPSR_OFFS 0x48 +#define FIQ_R8_OFFS 0x4C +#define FIQ_SP_OFFS 0x60 +#define ABT_R8_OFFS 0x68 +#define ABT_SPSR_OFFS 0x7C +#define ABT_SP_OFFS 0x80 +#define IRQ_R8_OFFS 0x88 +#define IRQ_SPSR_OFFS 0x9C +#define IRQ_SP_OFFS 0xA0 +#define UND_SPSR_OFFS 0xA8 +#define UND_SP_OFFS 0xAC +#define SYS_SPSR_OFFS 0xB4 +#define SYS_SP_OFFS 0xB8 + +#ifndef __ASSEMBLER__ +#define SLEEP_DATA_FINGERPRINT 0xdeadbeef +struct sleep_data { + u32 fingerprint; + u32 wake_addr; + u32 link_addr; + u32 mmuctl; + u32 mmuauxctl; + u32 mmucpaccess; + u32 mmuttb; + u32 mmupid; + u32 mmudomain; + u32 svc_r6; + u32 svc_r7; + u32 svc_r8; + u32 svc_r9; + u32 svc_r10; + u32 svc_r11; + u32 svc_r12; + u32 svc_sp; + u32 svc_spsr; + u32 fiq_spsr; + u32 fiq_r8; + u32 fiq_r9; + u32 fiq_r10; + u32 fiq_r11; + u32 fiq_r12; + u32 fiq_sp; + u32 fiq_lr; + u32 abt_r8; + u32 abt_r9; + u32 abt_r10; + u32 abt_r11; + u32 abt_r12; + u32 abt_spsr; + u32 abt_sp; + u32 abt_lr; + u32 irq_r8; + u32 irq_r9; + u32 irq_r10; + u32 irq_r11; + u32 irq_r12; + u32 irq_spsr; + u32 irq_sp; + u32 irq_lr; + u32 und_spsr; + u32 und_sp; + u32 und_lr; + u32 sys_spsr; + u32 sys_sp; + u32 sys_lr; + u32 pinmux[0x100]; + u32 icoll_ctrl; + union { + u32 prio[0x10]; + u32 intr[0x80]; + } icoll; + u32 clks[16]; + u32 old_c00; + u32 old_c04; +}; + +extern int mx2_s2ram_alloc_sz; +void mx28_cpu_suspend(void); +extern int mx28_standby_alloc_sz; +void mx28_cpu_standby(void); +void mxs_suspend_timer(void); +void mxs_resume_timer(void); + +void *iram_alloc(unsigned int size, unsigned long *dma_addr); +void iram_free(unsigned long addr, unsigned int size); +#endif /* __ASSEMBLER__ */ +#endif /* __PM_H__ */ diff --git a/arch/arm/mach-mx28/usb.h b/arch/arm/mach-mx28/usb.h new file mode 100644 index 000000000000..689603d4e7d6 --- /dev/null +++ b/arch/arm/mach-mx28/usb.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, + struct fsl_usb2_platform_data + *config); +extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable); +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff --git a/arch/arm/mach-mx28/usb_dr.c b/arch/arm/mach-mx28/usb_dr.c new file mode 100644 index 000000000000..dff6b35840f2 --- /dev/null +++ b/arch/arm/mach-mx28/usb_dr.c @@ -0,0 +1,570 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/gpio.h> + +#include <mach/irqs.h> +#include <mach/arc_otg.h> +#include "usb.h" +#include "mx28_pins.h" +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX) + +extern int clk_get_usecount(struct clk *clk); +static struct clk *usb_clk; +static struct clk *usb_phy_clk; +static struct platform_device *otg_host_pdev; + +/* Beginning of Common operation for DR port */ +void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this) +{ +} + +void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + /* USB_POWER_ENABLE_PIN have request at pin init*/ + if (pdata->phy_regs != USBPHY1_PHYS_ADDR) { + pr_debug("%s: on is %d\n", __func__, on); + gpio_direction_output(USB_POWER_ENABLE, on); + gpio_set_value(USB_POWER_ENABLE, on); + } +} + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int internal_phy_clk_already_on; +static void usbotg_internal_phy_clock_gate(bool on) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(USBPHY0_PHYS_ADDR); + if (on) { + internal_phy_clk_already_on += 1; + if (internal_phy_clk_already_on == 1) { + pr_debug ("%s, Clock on UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } + } else { + internal_phy_clk_already_on -= 1; + if (internal_phy_clk_already_on == 0) { + pr_debug ("%s, Clock off UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } + } + if (internal_phy_clk_already_on < 0) + printk(KERN_ERR "please check internal phy clock ON/OFF sequence \n"); +} + +static int usbotg_init_ext(struct platform_device *pdev) +{ + usb_clk = clk_get(NULL, "usb_clk0"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_phy_clk = clk_get(NULL, "usb_phy_clk0"); + clk_enable(usb_phy_clk); + clk_put(usb_phy_clk); + + usbotg_internal_phy_clock_gate(true); + return usbotg_init(pdev); +} + +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + usbotg_uninit(pdata); + + usbotg_internal_phy_clock_gate(false); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); +} + +static void usbotg_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_clk); + clk_enable(usb_phy_clk); + usbotg_internal_phy_clock_gate(on); + } else { + usbotg_internal_phy_clock_gate(on); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); + } + + pr_debug("usb_clk0_ref_count:%d, usb_phy_clk0_ref_count:%d\n", clk_get_usecount(usb_clk), clk_get_usecount(usb_phy_clk)); +} + +/* Below two macros are used at otg mode to indicate usb mode*/ +#define ENABLED_BY_HOST (0x1 << 0) +#define ENABLED_BY_DEVICE (0x1 << 1) +static u32 low_power_enable_src; /* only useful at otg mode */ +static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 tmp; + pr_debug("DR: %s, enable is %d\n", __func__, enable); + + if (enable) { + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp |= PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + + pr_debug("%s, Poweroff UTMI \n", __func__); + + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET); + + pr_debug ("%s, Polling UTMI enter suspend \n", __func__); + while (tmp & BM_USBPHY_CTRL_UTMI_SUSPENDM) + tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL); + } else { + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR); + + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp &= ~PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + } +} + +static void __phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable, int source) +{ + if (enable) { + low_power_enable_src |= source; +#ifdef CONFIG_USB_OTG + if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + pr_debug("phy lowpower enabled\n"); + enter_phy_lowpower_suspend(pdata, enable); + } +#else + enter_phy_lowpower_suspend(pdata, enable); +#endif + } else { + pr_debug("phy lowpower disable\n"); + enter_phy_lowpower_suspend(pdata, enable); + low_power_enable_src &= ~source; + } +} + +static void otg_wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + + pr_debug("%s, enable is %d\n", __func__, enable); + if (enable) { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + __raw_writel(BM_USBPHY_CTRL_ENIRQWAKEUP, phy_reg + HW_USBPHY_CTRL_SET); + } else { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + __raw_writel(BM_USBPHY_CTRL_ENIRQWAKEUP, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static u32 wakeup_irq_enable_src; /* only useful at otg mode */ +static void __wakeup_irq_enable(struct fsl_usb2_platform_data *pdata, bool on, int source) + { + /* otg host and device share the OWIE bit, only when host and device + * all enable the wakeup irq, we can enable the OWIE bit + */ + if (on) { +#ifdef CONFIG_USB_OTG + wakeup_irq_enable_src |= source; + if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + otg_wake_up_enable(pdata, on); + } +#else + otg_wake_up_enable(pdata, on); +#endif + } else { + otg_wake_up_enable(pdata, on); + wakeup_irq_enable_src &= ~source; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +/* The wakeup operation for DR port, it will clear the wakeup irq status + * and re-enable the wakeup + */ +static void usbotg_wakeup_event_clear(void) +{ + void __iomem *phy_reg = IO_ADDRESS(USBPHY0_PHYS_ADDR); + u32 wakeup_irq_bits; + + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + /* clear the wakeup interrupt status */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + } +} + +/* End of Common operation for DR port */ + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +/* Beginning of host related operation for DR port */ +static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(pdata, enable, ENABLED_BY_HOST); +} + +static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + __wakeup_irq_enable(pdata, enable, ENABLED_BY_HOST); + tmp = BM_USBPHY_CTRL_ENIDCHG_WKUP | BM_USBPHY_CTRL_ENDPDMCHG_WKUP; + /* host only care the ID change wakeup event */ + if (enable) { + pr_debug("DR: host wakeup enable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + pr_debug("DR: host wakeup disable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 wakeup_irq_bits, wakeup_req, otgsc; + + pr_debug("%s\n", __func__); + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + otgsc = __raw_readl(usb_reg + UOG_OTGSC); + + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) + wakeup_req = 1; + + /* if ID change sts, it is a host wakeup event */ + if (wakeup_req && (otgsc & OTGSC_IS_USB_ID)) { + pr_debug("otg host ID wakeup\n"); + /* if host ID wakeup, we must clear the b session change sts */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + __raw_writel(otgsc & (~OTGSC_IS_USB_ID), usb_reg + UOG_OTGSC); + return WAKEUP_EVENT_ID; + } + if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) { + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + pr_debug("otg host Remote wakeup\n"); + return WAKEUP_EVENT_DPDM; + } + return WAKEUP_EVENT_INVALID; +} + +static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _host_wakeup_enable(pdata, false); + _host_phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(otg_host_pdev); +} +/* End of host related operation for DR port */ +#endif /* CONFIG_USB_EHCI_ARC_OTG */ + + +#ifdef CONFIG_USB_GADGET_ARC +/* Beginning of device related operation for DR port */ +static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(pdata, enable, ENABLED_BY_DEVICE); +} + +static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + tmp = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | BM_USBPHY_CTRL_ENDPDMCHG_WKUP; + __wakeup_irq_enable(pdata, enable, ENABLED_BY_DEVICE); + /* if udc is not used by any gadget, we can not enable the vbus wakeup */ + if (!pdata->port_enables) { + __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR); + return; + } + if (enable) { + pr_debug("device wakeup enable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + pr_debug("device wakeup disable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } +} + +static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 wakeup_irq_bits, wakeup_req, otgsc; + + pr_debug("%s\n", __func__); + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + otgsc = __raw_readl(usb_reg + UOG_OTGSC); + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + wakeup_req = 1; + } + + /* if ID change sts, it is a host wakeup event */ + if (wakeup_req && (otgsc & OTGSC_STS_USB_ID) && (otgsc & OTGSC_IS_B_SESSION_VALID)) { + pr_debug("otg device wakeup\n"); + /* if host ID wakeup, we must clear the b session change sts */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + return WAKEUP_EVENT_VBUS; + } + + return WAKEUP_EVENT_INVALID; +} + +static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _device_wakeup_enable(pdata, false); + _device_phy_lowpower_suspend(pdata, false); +} + +/* end of device related operation for DR port */ +#endif /* CONFIG_USB_GADGET_ARC */ + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit_ext, + .usb_clock_for_pm = usbotg_clock_gate, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .phy_regs = USBPHY0_PHYS_ADDR, +}; + +/* + * OTG resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{} + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +static struct resource usbotg_wakeup_resources[] = { + { + .start = IRQ_USB0_WAKEUP, /*wakeup irq*/ + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_USB0, /* usb core irq */ + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxs_usbotg_wakeup_device = { + .name = "usb_wakeup", + .id = 1, + .num_resources = ARRAY_SIZE(usbotg_wakeup_resources), + .resource = usbotg_wakeup_resources, +}; + +static struct fsl_usb2_wakeup_platform_data usbdr_wakeup_config = { + .name = "DR wakeup", + .usb_clock_for_pm = usbotg_clock_gate, + .usb_wakeup_exhandle = usbotg_wakeup_event_clear, +}; + +static int __init usb_dr_init(void) +{ + struct platform_device *pdev; + + pr_debug("%s: \n", __func__); + dr_utmi_config.change_ahb_burst = 1; + dr_utmi_config.ahb_burst_mode = 0; + +#ifdef CONFIG_USB_OTG + dr_utmi_config.operating_mode = FSL_USB2_DR_OTG; + /* wake_up_enalbe is useless, just for usb_register_remote_wakeup execution*/ + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb DR: can't register otg device\n"); + else { + platform_device_add_data(&dr_otg_device, &dr_utmi_config, sizeof(dr_utmi_config)); + usbdr_wakeup_config.usb_pdata[0] = dr_otg_device.dev.platform_data; + } +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG + dr_utmi_config.operating_mode = DR_HOST_MODE; + dr_utmi_config.wake_up_enable = _host_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; + dr_utmi_config.wakeup_handler = host_wakeup_handler; + dr_utmi_config.is_wakeup_event = _is_host_wakeup; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + pdev = host_pdev_register(otg_resources, + ARRAY_SIZE(otg_resources), &dr_utmi_config); + if (pdev) { + usbdr_wakeup_config.usb_pdata[1] = pdev->dev.platform_data; + otg_host_pdev = pdev; + } else + printk(KERN_ERR "usb DR: can't alloc platform device for host\n"); +#endif + +#ifdef CONFIG_USB_GADGET_ARC + dr_utmi_config.operating_mode = DR_UDC_MODE; + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend; + dr_utmi_config.is_wakeup_event = _is_device_wakeup; + dr_utmi_config.wakeup_handler = device_wakeup_handler; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb DR: can't register udc device\n"); + else { + platform_device_add_data(&dr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config)); + usbdr_wakeup_config.usb_pdata[2] = dr_udc_device.dev.platform_data; + } +#endif + + mxs_usbotg_wakeup_device.dev.platform_data = &usbdr_wakeup_config; + + if (platform_device_register(&mxs_usbotg_wakeup_device)) + printk(KERN_ERR "usb DR wakeup device\n"); + else + printk(KERN_INFO "usb DR wakeup device is registered\n"); + + return 0; +} +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(usb_dr_init); +#else + subsys_initcall(usb_dr_init); +#endif diff --git a/arch/arm/mach-mx28/usb_h1.c b/arch/arm/mach-mx28/usb_h1.c new file mode 100644 index 000000000000..0c36d8f04130 --- /dev/null +++ b/arch/arm/mach-mx28/usb_h1.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/fsl_devices.h> +#include <mach/arc_otg.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/irqs.h> +#include "usb.h" + +extern int clk_get_usecount(struct clk *clk); +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +static struct clk *usb_clk; +static struct clk *usb_phy_clk; +static struct platform_device *h1_pdev; + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int internal_phy_clk_already_on; +static void usbh1_internal_phy_clock_gate(bool on) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(USBPHY1_PHYS_ADDR); + if (on) { + internal_phy_clk_already_on += 1; + if (internal_phy_clk_already_on == 1) { + pr_debug ("%s, Clock on UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } + } else { + internal_phy_clk_already_on -= 1; + if (internal_phy_clk_already_on == 0) { + pr_debug ("%s, Clock off UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } + } + if (internal_phy_clk_already_on < 0) + printk(KERN_ERR "please check internal phy clock ON/OFF sequence \n"); +} +static int fsl_usb_host_init_ext(struct platform_device *pdev) +{ + usb_clk = clk_get(NULL, "usb_clk1"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_phy_clk = clk_get(NULL, "usb_phy_clk1"); + clk_enable(usb_phy_clk); + clk_put(usb_phy_clk); + + usbh1_internal_phy_clock_gate(true); + return fsl_usb_host_init(pdev); +} + +static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + fsl_usb_host_uninit(pdata); + usbh1_internal_phy_clock_gate(false); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); +} + +static void usbh1_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_clk); + clk_enable(usb_phy_clk); + } else { + clk_disable(usb_phy_clk); + clk_disable(usb_clk); + } + pr_debug("usb_clk1_ref_count:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_clk), clk_get_usecount(usb_phy_clk)); +} + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + tmp = (BM_USBPHY_CTRL_ENIRQWAKEUP + | BM_USBPHY_CTRL_ENIDCHG_WKUP + | BM_USBPHY_CTRL_ENDPDMCHG_WKUP); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + tmp = (BM_USBPHY_CTRL_ENIRQWAKEUP + | BM_USBPHY_CTRL_ENIDCHG_WKUP + | BM_USBPHY_CTRL_ENDPDMCHG_WKUP); + + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) { + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp |= PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + + pr_debug("%s, Poweroff UTMI \n", __func__); + + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET); + + pr_debug ("%s, Polling UTMI enter suspend \n", __func__); + while (tmp & BM_USBPHY_CTRL_UTMI_SUSPENDM) + tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL); + } else { + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR); + + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp &= ~PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + } +} + +static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + pr_debug("host1, %s\n", __func__); + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && tmp) { + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + return !WAKEUP_EVENT_INVALID; + } else + return WAKEUP_EVENT_INVALID; +} + +static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _wake_up_enable(pdata, false); + _phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(h1_pdev); +} + +static void usbh1_wakeup_event_clear(void) +{ + void __iomem *phy_reg = IO_ADDRESS(USBPHY1_PHYS_ADDR); + u32 wakeup_irq_bits; + + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + /* clear the wakeup interrupt status */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + } +} +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init_ext, + .platform_uninit = fsl_usb_host_uninit_ext, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .usb_clock_for_pm = usbh1_clock_gate, + .wake_up_enable = _wake_up_enable, + .phy_lowpower_suspend = _phy_lowpower_suspend, + .is_wakeup_event = _is_usbh1_wakeup, + .wakeup_handler = h1_wakeup_handler, + .phy_regs = USBPHY1_PHYS_ADDR, +}; + +static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = { + .name = "USBH1 wakeup", + .usb_clock_for_pm = usbh1_clock_gate, + .usb_pdata = {&usbh1_config, NULL, NULL}, + .usb_wakeup_exhandle = usbh1_wakeup_event_clear, +}; + +/* The resources for kinds of usb devices */ +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USBCTRL1_PHYS_ADDR), + .end = (u32) (USBCTRL1_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbh1_wakeup_resources[] = { + { + .start = IRQ_USB1_WAKEUP, /*wakeup irq*/ + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_USB1, + .flags = IORESOURCE_IRQ,/* usb core irq */ + }, +}; + +struct platform_device mxs_usbh1_wakeup_device = { + .name = "usb_wakeup", + .id = 2, + .num_resources = ARRAY_SIZE(usbh1_wakeup_resources), + .resource = usbh1_wakeup_resources, +}; + +static int __init usbh1_init(void) +{ + struct platform_device *pdev; + + usbh1_config.wakeup_pdata = &usbh1_wakeup_config; + pdev = host_pdev_register(usbh1_resources, + ARRAY_SIZE(usbh1_resources), &usbh1_config); + + h1_pdev = pdev; + pr_debug("%s: \n", __func__); + + /* the platform device(usb h1)'s pdata address has changed */ + usbh1_wakeup_config.usb_pdata[0] = pdev->dev.platform_data; + mxs_usbh1_wakeup_device.dev.platform_data = &usbh1_wakeup_config; + + if (platform_device_register(&mxs_usbh1_wakeup_device)) + printk(KERN_ERR "usb h1 wakeup device\n"); + else + printk(KERN_INFO "usb h1 wakeup device is registered\n"); + + return 0; +} +module_init(usbh1_init); |