diff options
author | Alison Wang <b18965@freescale.com> | 2012-07-26 15:24:38 +0800 |
---|---|---|
committer | Justin Waters <justin.waters@timesys.com> | 2012-09-12 16:49:39 -0400 |
commit | e426e71b4fe2b2907cba29f7be472e68efe2e47e (patch) | |
tree | c29b3a4647969a83e808803dbcb2d665cd0b0f30 /arch/arm/mach-mvf/crm_regs.h | |
parent | f01398b9af3cc8ad75bb60628753dc517a952c5a (diff) |
ENGR00180931-1 mvf: add MSL support for MVF platform
Add MSL support for MVF platform.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Diffstat (limited to 'arch/arm/mach-mvf/crm_regs.h')
-rw-r--r-- | arch/arm/mach-mvf/crm_regs.h | 536 |
1 files changed, 536 insertions, 0 deletions
diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h new file mode 100644 index 000000000000..744dbfff2165 --- /dev/null +++ b/arch/arm/mach-mvf/crm_regs.h @@ -0,0 +1,536 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MVF_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MVF_CRM_REGS_H__ + +/* IOMUXC */ +#define MXC_IOMUXC_BASE MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR) +#define IOMUXC_GPR0 (MXC_IOMUXC_BASE + 0x00) +#define IOMUXC_GPR1 (MXC_IOMUXC_BASE + 0x04) +#define IOMUXC_GPR2 (MXC_IOMUXC_BASE + 0x08) +#define IOMUXC_GPR3 (MXC_IOMUXC_BASE + 0x0C) +#define IOMUXC_GPR4 (MXC_IOMUXC_BASE + 0x10) +#define IOMUXC_GPR5 (MXC_IOMUXC_BASE + 0x14) +#define IOMUXC_GPR6 (MXC_IOMUXC_BASE + 0x18) +#define IOMUXC_GPR7 (MXC_IOMUXC_BASE + 0x1C) +#define IOMUXC_GPR8 (MXC_IOMUXC_BASE + 0x20) +#define IOMUXC_GPR9 (MXC_IOMUXC_BASE + 0x24) +#define IOMUXC_GPR10 (MXC_IOMUXC_BASE + 0x28) +#define IOMUXC_GPR11 (MXC_IOMUXC_BASE + 0x2C) +#define IOMUXC_GPR12 (MXC_IOMUXC_BASE + 0x30) +#define IOMUXC_GPR13 (MXC_IOMUXC_BASE + 0x34) + +/* DDRMC */ +#define MXC_DDRMC_BASE MVF_IO_ADDRESS(DDRMC_BASE_ADDR) +#define DDRMC_CR00_OFFSET (MXC_DDRMC_BASE + 0x00) +/* + * dram class: b0101->lpddr2 + * b0110->ddr3 + */ +#define DDRMC_MDMISC_DDR_TYPE_MASK (0x7 << 8) +#define DDRMC_MDMISC_DDR_TYPE_OFFSET (8) + +/* PLLs */ +#define MXC_PLL_BASE MVF_IO_ADDRESS(ANADIG_BASE_ADDR) +#define PLL1_SYS_BASE_ADDR (MXC_PLL_BASE + 0x270) +#define PLL2_528_BASE_ADDR (MXC_PLL_BASE + 0x30) +#define PLL3_480_USB1_BASE_ADDR (MXC_PLL_BASE + 0x10) +#define PLL4_AUDIO_BASE_ADDR (MXC_PLL_BASE + 0x70) +#define PLL6_VIDEO_BASE_ADDR (MXC_PLL_BASE + 0xA0) +#define PLL3_480_USB2_BASE_ADDR (MXC_PLL_BASE + 0x20) +#define PLL5_ENET_BASE_ADDR (MXC_PLL_BASE + 0xE0) +#define PFD_480_BASE_ADDR (MXC_PLL_BASE + 0xF0) +#define PFD_528_BASE_ADDR (MXC_PLL_BASE + 0x100) +#define PFD_528SYS_BASE_ADDR (MXC_PLL_BASE + 0x2B0) +#define ANADIG_MISC0_REG (MXC_PLL_BASE + 0x150) +#define ANADIG_MISC1_REG (MXC_PLL_BASE + 0x160) +#define PLL_PFD_480_USB1 (MXC_PLL_BASE + 0xF0) +#define ANADIG_USB1_VBUS_DETECT (MXC_PLL_BASE + 0x1A0) +#define ANADIG_USB1_CHRG_DETECT (MXC_PLL_BASE + 0x1B0) +#define ANADIG_USB1_VBUS_DETECT_STATUS (MXC_PLL_BASE + 0x1C0) +#define ANADIG_USB1_CHRG_DETECT_STATUS (MXC_PLL_BASE + 0x1D0) +#define ANADIG_USB1_LOOPBACK (MXC_PLL_BASE + 0x1E0) +#define ANADIG_USB1_MISC (MXC_PLL_BASE + 0x1F0) +#define ANADIG_USB2_VBUS_DETECT (MXC_PLL_BASE + 0x200) +#define ANADIG_USB2_CHRG_DETECT (MXC_PLL_BASE + 0x210) +#define ANADIG_USB2_VBUS_DETECT_STATUS (MXC_PLL_BASE + 0x220) +#define ANADIG_USB2_CHRG_DETECT_STATUS (MXC_PLL_BASE + 0x230) +#define ANADIG_USB2_LOOPBACK (MXC_PLL_BASE + 0x240) +#define ANADIG_USB2_MISC (MXC_PLL_BASE + 0x250) +#define PLL_LOCK_STATUS (MXC_PLL_BASE + 0x2C0) +/* + * MXC_PLL_BASE=0x40050000 + * 32-bits registers + */ +#define USBPHY1_PWD (MXC_PLL_BASE + 0x0800 + 0x0) +#define USBPHY1_TX (MXC_PLL_BASE + 0x0800 + 0x10) +#define USBPHY1_RX (MXC_PLL_BASE + 0x0800 + 0x20) +#define USBPHY1_CTRL (MXC_PLL_BASE + 0x0800 + 0x30) +#define USBPHY1_STATUS (MXC_PLL_BASE + 0x0800 + 0x40) +#define USBPHY1_DEBUG (MXC_PLL_BASE + 0x0800 + 0x50) +#define USBPHY1_DEBUG0_STATUS (MXC_PLL_BASE + 0x0800 + 0x60) +#define USBPHY1_DEBUG1 (MXC_PLL_BASE + 0x0800 + 0x70) +#define USBPHY1_VERSION (MXC_PLL_BASE + 0x0800 + 0x80) +#define USBPHY1_IP (MXC_PLL_BASE + 0x0800 + 0x90) + +#define USBPHY2_PWD (MXC_PLL_BASE + 0x0C00 + 0x0) +#define USBPHY2_TX (MXC_PLL_BASE + 0x0C00 + 0x10) +#define USBPHY2_RX (MXC_PLL_BASE + 0x0C00 + 0x20) +#define USBPHY2_CTRL (MXC_PLL_BASE + 0x0C00 + 0x30) +#define USBPHY2_STATUS (MXC_PLL_BASE + 0x0C00 + 0x40) +#define USBPHY2_DEBUG (MXC_PLL_BASE + 0x0C00 + 0x50) +#define USBPHY2_DEBUG0_STATUS (MXC_PLL_BASE + 0x0C00 + 0x60) +#define USBPHY2_DEBUG1 (MXC_PLL_BASE + 0x0C00 + 0x70) +#define USBPHY2_VERSION (MXC_PLL_BASE + 0x0C00 + 0x80) +#define USBPHY2_IP (MXC_PLL_BASE + 0x0C00 + 0x90) + + +#define ANATOP_LVDS_CLK1_SRC_SATA 0xB +#define ANATOP_LVDS_CLK1_OBEN_MASK 0x400 +#define ANATOP_LVDS_CLK1_IBEN_MASK 0x1000 + +#define PLL_SETREG_OFFSET 0x4 +#define PLL_CLRREG_OFFSET 0x8 +#define PLL_TOGGLE_OFFSET 0x0C +#define PLL_NUM_DIV_OFFSET 0x10 +#define PLL_DENOM_DIV_OFFSET 0x20 +#define PLL_528_SS_OFFSET 0x10 +#define PLL_528_NUM_DIV_OFFSET 0x20 +#define PLL_528_DENOM_DIV_OFFSET 0x30 + +/* Common PLL register bit defines. */ +#define ANADIG_PLL_LOCK (1 << 31) +#define ANADIG_PLL_BYPASS (1 << 16) +#define ANADIG_PLL_BYPASS_CLK_SRC_MASK (0x1 << 14) +#define ANADIG_PLL_BYPASS_CLK_SRC_OFFSET (14) +#define ANADIG_PLL_ENABLE (1 << 13) +#define ANADIG_PLL_POWER_DOWN (1 << 12) +#define ANADIG_PLL_HOLD_RING_OFF (1 << 11) + +/* PLL1_SYS defines */ +#define ANADIG_PLL_SYS_DIV_SELECT_MASK (0x7F) +#define ANADIG_PLL_SYS_DIV_SELECT_OFFSET (0) + +/* PLL2_528 defines */ +#define ANADIG_PLL_528_DIV_SELECT (1) + +/* PLL3_480 defines. */ +#define ANADIG_PLL_480_EN_USB_CLKS (1 << 6) +#define ANADIG_PLL_480_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_480_DIV_SELECT_OFFSET (0) + +/* PLL4_AUDIO PLL6_VIDEO defines. */ +#define ANADIG_PLL_AV_DIV_SELECT_MASK (0x7F) +#define ANADIG_PLL_AV_DIV_SELECT_OFFSET (0) +#define ANADIG_PLL_AV_TEST_DIV_SEL_MASK (0x180000) +#define ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET (19) + +/* PLL5_ENET defines. */ +#define ANADIG_PLL_ENET_LOCK (1 << 31) +#define ANADIG_PLL_ENET_EN_SATA (1 << 20) +#define ANADIG_PLL_ENET_EN_PCIE (1 << 19) +#define ANADIG_PLL_ENET_BYPASS (1 << 16) +#define ANADIG_PLL_ENET_EN (1 << 13) +#define ANADIG_PLL_ENET_POWER_DOWN (1 << 12) +#define ANADIG_PLL_ENET_DIV_SELECT_MASK (0x3) +#define ANADIG_PLL_ENET_DIV_SELECT_OFFSET (0) + +/* PFD register defines. */ +#define ANADIG_PFD_FRAC_MASK 0x3F +#define ANADIG_PFD3_CLKGATE (1 << 31) +#define ANADIG_PFD3_STABLE (1 << 30) +#define ANADIG_PFD3_FRAC_OFFSET 24 +#define ANADIG_PFD2_CLKGATE (1 << 23) +#define ANADIG_PFD2_STABLE (1 << 22) +#define ANADIG_PFD2_FRAC_OFFSET 16 +#define ANADIG_PFD1_CLKGATE (1 << 15) +#define ANADIG_PFD1_STABLE (1 << 14) +#define ANADIG_PFD1_FRAC_OFFSET 8 +#define ANADIG_PFD0_CLKGATE (1 << 7) +#define ANADIG_PFD0_STABLE (1 << 6) +#define ANADIG_PFD0_FRAC_OFFSET 0 + +/* ANATOP Regulator/LDO defines */ +#define ANADIG_REG_RAMP_RATE_MASK 0x03 +#define ANADIG_REG_RAMP_RATE_OFFSET (0x3 << 27) +#define ANADIG_REG_ADJUST_MASK 0xF +#define ANADIG_REG_TARGET_MASK 0x1F +#define ANADIG_REG2_SOC_ADJUST_OFFSET 23 +#define ANADIG_REG2_SOC_TARGET_OFFSET 18 +#define ANADIG_REG1_PU_ADJUST_OFFSET 14 +#define ANADIG_REG1_PU_TARGET_OFFSET 9 +#define ANADIG_REG0_CORE_ADJUST_OFFSET 5 +#define ANADIG_REG0_CORE_TARGET_OFFSET 0 + +/* ANA MISC0 register defines */ +#define ANADIG_MISC0_OSC_XTALOK_EN (1 << 17) +#define ANADIG_MISC0_OSC_XTALOK (1 << 16) +#define ANADIG_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) +#define ANADIG_MISC0_STOP_MODE_CONFIG (1 << 11) +#define ANADIG_MISC0_REFTOP_VBGUP (1 << 7) +#define ANADIG_MISC0_REFTOP_SELBIASOFF (1 << 3) +#define ANADIG_MISC0_REFTOP_LOWPOWER (1 << 2) +#define ANADIG_MISC0_REFTOP_PWDVBGUP (1 << 1) +#define ANADIG_MISC0_REFTOP_PWD (1 << 0) + + +#define MXC_CCM_BASE MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR) + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x0c) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x1c) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x2c) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x3c) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x4c) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x5c) +#define MXC_CCM_CCGR8 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CCGR9 (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR10 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR11 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CMEOR0 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CMEOR1 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CMEOR2 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CMEOR3 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CMEOR4 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR5 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CPPDSR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CCOWR (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CCPGR0 (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CCPGR1 (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CCPGR2 (MXC_CCM_BASE + 0x98) +#define MXC_CCM_CCPGR3 (MXC_CCM_BASE + 0x9C) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_FIRC_EN (1 << 16) +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSC_READY (1 << 5) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_PLL3_PFD4_EN (1 << 31) +#define MXC_CCM_CCSR_PLL3_PFD3_EN (1 << 30) +#define MXC_CCM_CCSR_PLL3_PFD2_EN (1 << 29) +#define MXC_CCM_CCSR_PLL3_PFD1_EN (1 << 28) +#define MXC_CCM_CCSR_DAP_EN (1 << 24) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET (19) +#define MXC_CCM_CCSR_PLL2_PFD_CLK_SLE_MASK (0x7 << 19) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET (16) +#define MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) +#define MXC_CCM_CCSR_PLL2_PFD4_EN (1 << 15) +#define MXC_CCM_CCSR_PLL2_PFD3_EN (1 << 14) +#define MXC_CCM_CCSR_PLL2_PFD2_EN (1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD1_EN (1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD4_EN (1 << 11) +#define MXC_CCM_CCSR_PLL1_PFD3_EN (1 << 10) +#define MXC_CCM_CCSR_PLL1_PFD2_EN (1 << 9) +#define MXC_CCM_CCSR_PLL1_PFD1_EN (1 << 8) +#define MXC_CCM_CCSR_DDRC_CLK_SEL_OFFSET (6) +#define MXC_CCM_CCSR_DDRC_CLK_SEL_MASK (1 << 6) +#define MXC_CCM_CCSR_FAST_CLK_SEL_OFFSET (5) +#define MXC_CCM_CCSR_FAST_CLK_SEL_MASK (1 << 5) +#define MXC_CCM_CCSR_SLOW_CLK_SEL_OFFSET (4) +#define MXC_CCM_CCSR_SLOW_CLK_SEL_MASK (1 << 4) +#define MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET (3) +#define MXC_CCM_CCSR_CA5_CLK_SEL_MASK (1 << 3) +#define MXC_CCM_CCSR_SYS_CLK_SEL_OFFSET (0) +#define MXC_CCM_CCSR_SYS_CLK_SEL_MASK (0x7) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_FLEX_CLK_DIV_OFFSET (22) +#define MXC_CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22) +#define MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET (21) +#define MXC_CCM_CACRR_PLL3_CLK_DIV_OFFSET (20) +#define MXC_CCM_CACRR_PLL1_CLK_DIV_OFFSET (16) +#define MXC_CCM_CACRR_PLL1_CLK_DIV_MASK (0x3 << 16) +#define MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET (11) +#define MXC_CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_OFFSET (6) +#define MXC_CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6) +#define MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET (3) +#define MXC_CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) +#define MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET (0) +#define MXC_CCM_CACRR_ARM_CLK_DIV_MASK (0x7) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL_OFFSET (29) +#define MXC_CCM_CSCMR1_DCU1_CLK_SEL_MASK (1 << 29) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_DCU0_CLK_SEL_MASK (1 << 28) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESAI_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC0_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_GCC_CLK_SEL_OFFSET (1 << 14) +#define MXC_CCM_CSCMR1_NFC_CLK_SEL_OFFSET (1 << 12) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (1 << 10) +#define MXC_CCM_CSCMR1_VADC_CLK_SEL_OFFSET (1 << 8) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR1_SAI3_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SAI1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR1_SAI0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_FTM3_CLK_EN (0x1 << 28) +#define MXC_CCM_CSCDR1_FTM2_CLK_EN (0x1 << 27) +#define MXC_CCM_CSCDR1_FTM1_CLK_EN (0x1 << 26) +#define MXC_CCM_CSCDR1_FTM0_CLK_EN (0x1 << 25) +#define MXC_CCM_CSCDR1_RMII_CLK_EN (0x1 << 24) +#define MXC_CCM_CSCDR1_ENET_TS_EN (0x1 << 23) +#define MXC_CCM_CSCDR1_VADC_EN (0x1 << 22) +#define MXC_CCM_CSCDR1_VADC_DIV_OFFSET 20 +#define MXC_CCM_CSCDR1_VADC_DIV_MASK (0x3 << 20) +#define MXC_CCM_CSCDR1_SAI3_EN (0x1 << 19) +#define MXC_CCM_CSCDR1_SAI2_EN (0x1 << 18) +#define MXC_CCM_CSCDR1_SAI1_EN (0x1 << 17) +#define MXC_CCM_CSCDR1_SAI0_EN (0x1 << 16) +#define MXC_CCM_CSCDR1_SAI3_DIV_OFFSET (12) +#define MXC_CCM_CSCDR1_SAI3_DIV_MASK (0xF << 12) +#define MXC_CCM_CSCDR1_SAI2_DIV_OFFSET (8) +#define MXC_CCM_CSCDR1_SAI2_DIV_MASK (0xF << 8) +#define MXC_CCM_CSCDR1_SAI1_DIV_OFFSET (4) +#define MXC_CCM_CSCDR1_SAI1_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR1_SAI0_DIV_OFFSET (0) +#define MXC_CCM_CSCDR1_SAI0_DIV_MASK (0xF << 0) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ESAI_EN (0x1 << 30) +#define MXC_CCM_CSCDR2_ESDHC1_EN (0x1 << 29) +#define MXC_CCM_CSCDR2_ESDHC0_EN (0x1 << 28) +#define MXC_CCM_CSCDR2_ESAI_DIV_MASK (0xF << 24) +#define MXC_CCM_CSCDR2_ESAI_DIV_OFFSET (24) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_MASK (0xF << 20) +#define MXC_CCM_CSCDR2_ESDHC1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_MASK (0xF << 16) +#define MXC_CCM_CSCDR2_ESDHC0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR2_NFC_CLK_INV (0x1 << 14) +#define MXC_CCM_CSCDR2_NFC_FRAC_DIV_EN (0x1 << 13) +#define MXC_CCM_CSCDR2_CAN1_EN (0x1 << 12) +#define MXC_CCM_CSCDR2_CAN0_EN (0x1 << 11) +#define MXC_CCM_CSCDR2_GPU_EN (0x1 << 10) +#define MXC_CCM_CSCDR2_NFC_EN (0x1 << 9) +#define MXC_CCM_CSCDR2_SPDIF_EN (0x1 << 8) +#define MXC_CCM_CSCDR2_NFC_FRAC_OFFSET (4) +#define MXC_CCM_CSCDR2_NFC_DIV_MASK (0xF << 4) +#define MXC_CCM_CSCDR2_SPDIF_DIV_OFFSET (0) +#define MXC_CCM_CSCDR2_SPDIF_DIV_MASK (0xF) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_SWO_EN (0x1 << 28) +#define MXC_CCM_CSCDR3_SWO_DIV (0x1 << 27) +#define MXC_CCM_CSCDR3_TRACE_EN (0x1 << 26) +#define MXC_CCM_CSCDR3_TRACE_DIV_MASK (0x3 << 24) +#define MXC_CCM_CSCDR3_TRACE_DIV_OFFSET (24) +#define MXC_CCM_CSCDR3_DCU1_EN (0x1 << 23) +#define MXC_CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) +#define MXC_CCM_CSCDR3_DCU1_DIV_OFFSET (20) +#define MXC_CCM_CSCDR3_DCU0_EN (0x1 << 19) +#define MXC_CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_DCU0_DIV_OFFSET (16) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) +#define MXC_CCM_CSCDR3_NFC_PRE_DIV_OFFSET (13) +#define MXC_CCM_CSCDR3_QSPI1_EN (0x1 << 12) +#define MXC_CCM_CSCDR3_QSPI1_DIV (0x1 << 11) +#define MXC_CCM_CSCDR3_QSPI1_X2_DIV (0x1 << 10) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_MASK (0x3 << 8) +#define MXC_CCM_CSCDR3_QSPI1_X4_DIV_OFFSET (8) +#define MXC_CCM_CSCDR3_QSPI0_EN (0x1 << 4) +#define MXC_CCM_CSCDR3_QSPI0_DIV (0x1 << 3) +#define MXC_CCM_CSCDR3_QSPI0_X2_DIV (0x1 << 2) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_OFFSET (0) +#define MXC_CCM_CSCDR3_QSPI0_X4_DIV_MASK (0x3) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_SWO_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR2_TRACE_CLK_SEL (1 << 18) +#define MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL (1 << 17) +#define MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL (1 << 16) +#define MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL (1 << 15) +#define MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL (1 << 14) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR2_FTM1_EXT_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CSCMR2_FTM0_EXT_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR2_RMII_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_MASK (0x7) +#define MXC_CCM_CSCMR2_ENET_TS_CLK_SEL_OFFSET (0) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_MASK (0x7F) +#define MXC_CCM_CSCDR4_SNVS_CLK_DIV_OFFSET (0) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_M_L2CC_IDLE (1 << 25) +#define MXC_CCM_CLPCR_M_SCU_IDLE (1 << 24) +#define MXC_CCM_CLPCR_M_CORE1_WFI (1 << 23) +#define MXC_CCM_CLPCR_M_CORE0_WFI (1 << 22) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) +#define MXC_CCM_CLPCR_ANATOP_STOP_MODE (1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) +#define MXC_CCM_CLPCR_SBYOS (1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_LPM (1 << 5) + +/* CISR */ +#define MXC_CCM_CISR_COSC_READY (1 << 6) +#define MXC_CCM_CISR_LRF_PLL4 (1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (1 << 2) +#define MXC_CCM_CISIR_LRF_PLL2 (1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (1) + +/* CIMR */ +#define MXC_CCM_CIMR_COSC_READY (1 << 6) +#define MXC_CCM_CIMR_LRF_PLL4 (1 << 3) +#define MXC_CCM_CIMR_LRF_PLL3 (1 << 2) +#define MXC_CCM_CIMR_LRF_PLL2 (1 << 1) +#define MXC_CCM_CIMR_LRF_PLL1 (1) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG (1 << 4) +#define MXC_CCM_CGPR_QSPI1_ACCZ (1 << 1) +#define MXC_CCM_CGPR_QSPI0_ACCZ (1) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGRx_CG_MASK 0x3 +#define MXC_CCM_CCGRx_MOD_OFF 0x0 +#define MXC_CCM_CCGRx_MOD_ALWAYS_ON 0x2 +#define MXC_CCM_CCGRx_MOD_ON 0x3 +#define MXC_CCM_CCGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGRx_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) + +#define MXC_CCM_CCGRx_CG114_OFFSET 30 + +#define MXC_CCM_CCGRx_CG15_OFFSET 30 +#define MXC_CCM_CCGRx_CG14_OFFSET 28 +#define MXC_CCM_CCGRx_CG13_OFFSET 26 +#define MXC_CCM_CCGRx_CG12_OFFSET 24 +#define MXC_CCM_CCGRx_CG11_OFFSET 22 +#define MXC_CCM_CCGRx_CG10_OFFSET 20 +#define MXC_CCM_CCGRx_CG9_OFFSET 18 +#define MXC_CCM_CCGRx_CG8_OFFSET 16 +#define MXC_CCM_CCGRx_CG7_OFFSET 14 +#define MXC_CCM_CCGRx_CG6_OFFSET 12 +#define MXC_CCM_CCGRx_CG5_OFFSET 10 +#define MXC_CCM_CCGRx_CG4_OFFSET 8 +#define MXC_CCM_CCGRx_CG3_OFFSET 6 +#define MXC_CCM_CCGRx_CG2_OFFSET 4 +#define MXC_CCM_CCGRx_CG1_OFFSET 2 +#define MXC_CCM_CCGRx_CG0_OFFSET 0 + +/* CMEOR */ + +/* CPPDSR */ +#define MXC_CCM_CPPDSR_PLL3_PFD4_STAT (0x1 << 11) +#define MXC_CCM_CPPDSR_PLL3_PFD3_STAT (0x1 << 10) +#define MXC_CCM_CPPDSR_PLL3_PFD2_STAT (0x1 << 9) +#define MXC_CCM_CPPDSR_PLL3_PFD1_STAT (0x1 << 8) +#define MXC_CCM_CPPDSR_PLL2_PFD4_STAT (0x1 << 7) +#define MXC_CCM_CPPDSR_PLL2_PFD3_STAT (0x1 << 6) +#define MXC_CCM_CPPDSR_PLL2_PFD2_STAT (0x1 << 5) +#define MXC_CCM_CPPDSR_PLL2_PFD1_STAT (0x1 << 4) +#define MXC_CCM_CPPDSR_PLL1_PFD4_STAT (0x1 << 3) +#define MXC_CCM_CPPDSR_PLL1_PFD3_STAT (0x1 << 2) +#define MXC_CCM_CPPDSR_PLL1_PFD2_STAT (0x1 << 1) +#define MXC_CCM_CPPDSR_PLL1_PFD1_STAT (0x1) + + +/* CCOWR */ +#define MXC_CCM_CCOWR_AUX_CORE_WKUP (0x1 << 16) + +/* CCPGR */ +#define MXC_CCM_CCPGRx_PPCG_MASK 0x3 +#define MXC_CCM_CCPGRx_MOD_OFF 0x0 +#define MXC_CCM_CCPGRx_MOD_ALWAYS_ON 0x2 +#define MXC_CCM_CCPGRx_MOD_ON 0x3 +#define MXC_CCM_CCPGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCPGRx_PPCG15_MASK (0x3 << 30) +#define MXC_CCM_CCPGRx_PPCG14_MASK (0x3 << 28) +#define MXC_CCM_CCPGRx_PPCG13_MASK (0x3 << 26) +#define MXC_CCM_CCPGRx_PPCG12_MASK (0x3 << 24) +#define MXC_CCM_CCPGRx_PPCG11_MASK (0x3 << 22) +#define MXC_CCM_CCPGRx_PPCG10_MASK (0x3 << 20) +#define MXC_CCM_CCPGRx_PPCG9_MASK (0x3 << 18) +#define MXC_CCM_CCPGRx_PPCG8_MASK (0x3 << 16) +#define MXC_CCM_CCPGRx_PPCG7_MASK (0x3 << 14) +#define MXC_CCM_CCPGRx_PPCG5_MASK (0x3 << 10) +#define MXC_CCM_CCPGRx_PPCG4_MASK (0x3 << 8) +#define MXC_CCM_CCPGRx_PPCG3_MASK (0x3 << 6) +#define MXC_CCM_CCPGRx_PPCG2_MASK (0x3 << 4) +#define MXC_CCM_CCPGRx_PPCG1_MASK (0x3 << 2) +#define MXC_CCM_CCPGRx_PPCG0_MASK (0x3 << 0) + +#define MXC_CCM_CCPGRx_PPCG15_OFFSET 30 +#define MXC_CCM_CCPGRx_PPCG14_OFFSET 28 +#define MXC_CCM_CCPGRx_PPCG13_OFFSET 26 +#define MXC_CCM_CCPGRx_PPCG12_OFFSET 24 +#define MXC_CCM_CCPGRx_PPCG11_OFFSET 22 +#define MXC_CCM_CCPGRx_PPCG10_OFFSET 20 +#define MXC_CCM_CCPGRx_PPCG9_OFFSET 18 +#define MXC_CCM_CCPGRx_PPCG8_OFFSET 16 +#define MXC_CCM_CCPGRx_PPCG7_OFFSET 14 +#define MXC_CCM_CCPGRx_PPCG6_OFFSET 12 +#define MXC_CCM_CCPGRx_PPCG5_OFFSET 10 +#define MXC_CCM_CCPGRx_CG4_OFFSET 8 +#define MXC_CCM_CCPGRx_PCG3_OFFSET 6 +#define MXC_CCM_CCPGRx_PPCG2_OFFSET 4 +#define MXC_CCM_CCPGRx_PPCG1_OFFSET 2 +#define MXC_CCM_CCPGRx_PPCG0_OFFSET 0 + +#endif /* __ARCH_ARM_MACH_MVF_CRM_REGS_H__ */ |