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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 22:06:36 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-19 22:06:36 +0100
commit809b4e00baf006a990a73329ba381d536c6fa277 (patch)
treee949e0efd019d6f932537aba762792b07a84351c /arch/arm/common
parenta0a55682b83fd5f012afadcf415b030d7424ae68 (diff)
parent79a94c3538bda6869d7bb150b5e02dd3a72314dd (diff)
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/gic.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7dfa9a85bc0c..ada6359160eb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
/*
* Routines to acknowledge, disable and enable interrupts
- *
- * Linux assumes that when we're done with an interrupt we need to
- * unmask it, in the same way we need to unmask an interrupt when
- * we first enable it.
- *
- * The GIC has a separate notion of "end of interrupt" to re-enable
- * an interrupt after handling, in order to support hardware
- * prioritisation.
- *
- * We can make the GIC behave in the way that Linux expects by making
- * our "acknowledge" routine disable the interrupt, then mark it as
- * complete.
*/
static void gic_ack_irq(unsigned int irq)
{
- u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
- writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}