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authorOlof Johansson <olof@lixom.net>2012-03-13 17:38:09 -0700
committerOlof Johansson <olof@lixom.net>2012-03-13 17:38:09 -0700
commitae0b82504e515fdb9bc23c0b770d2b30efd49dc9 (patch)
tree665d1f26b32f9e68346a9529388fbadec519e865 /arch/arm/Kconfig
parentf7c8faedf98aa5ec372e0191078ac7fe1e7fb067 (diff)
parenta6e24019468009a21b674e392d74283a90f415dd (diff)
Merge branch 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas into next/soc
* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas: (234 commits) ARM: shmobile: remove additional __io() macro use ARM: mach-shmobile: default to no earlytimer ARM: mach-shmobile: r8a7779 and Marzen timer rework ARM: mach-shmobile: r8a7740 and Bonito timer rework ARM: mach-shmobile: sh73a0, AG5EVM and Kota2 timer rework ARM: mach-shmobile: sh7372, AP4EVB and Mackerel timer rework ARM: mach-shmobile: sh7377 and G4EVM timer rework ARM: mach-shmobile: sh7367 and G3EVM timer rework ARM: mach-shmobile: add shmobile_earlytimer_init() ARM: mach-shmobile: Move sh7372 AP4EVB external clk setup ARM: mach-shmobile: Move sh7372 Mackerel external clk setup ARM: mach-shmobile: rename clk_init() to shmobile_clk_init() ARM: mach-shmobile: r8a7779 L2 cache support ARM: mach-shmobile: r8a7779 map_io and init_early update ARM: mach-shmobile: r8a7740 map_io and init_early update ARM: mach-shmobile: sh73a0 map_io and init_early update ARM: mach-shmobile: sh7372 map_io and init_early update ARM: mach-shmobile: sh7377 map_io and init_early update ARM: mach-shmobile: sh7367 map_io and init_early update sh: remove clk_ops ... (includes an update to v3.3-rc7) Conflicts: arch/arm/mach-omap2/id.c
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a5436ef9397..0937f427623b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1281,7 +1281,7 @@ config ARM_ERRATA_743622
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
- (r2p0..r2p2) erratum. Under very rare conditions, a faulty
+ (r2p*) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer