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author | Ingo Molnar <mingo@kernel.org> | 2019-07-08 18:04:41 +0200 |
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committer | Ingo Molnar <mingo@kernel.org> | 2019-07-08 18:04:41 +0200 |
commit | 552a031ba12a4236be107a5b082a399237758a5d (patch) | |
tree | a2bcdeb651b360013dbb654bbcd61dbaf51e0331 /Documentation | |
parent | f584dd32edc5d4400d7ceb92111a89f0c1f6651f (diff) | |
parent | 0ecfebd2b52404ae0c54a878c872bb93363ada36 (diff) |
Merge tag 'v5.2' into perf/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 27f02ec4bb45..f97a4ecd7b91 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -152,17 +152,19 @@ examples: - | // Example 2: Spike ISA Simulator with 1 Hart cpus { - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv48"; - interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; ... |