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authorAdrian Hunter <adrian.hunter@intel.com>2015-09-25 16:15:34 +0300
committerArnaldo Carvalho de Melo <acme@redhat.com>2015-09-28 16:44:31 -0300
commit9992c2d50a73f442653968a98a9e5f3bf4e769e9 (patch)
treea0506fd29d4af79483eaec038847c2d675e70187 /Documentation/mips
parentd062ac16f53d1a24047bcc9eded5514a71c363b8 (diff)
perf intel-pt: Fix potential loop forever
TSC packets contain only 7 bytes of TSC. The 8th byte is assumed to change so infrequently that its value can be inferred. However the logic must cater for a 7 byte wraparound, which it does by adding 1 to the top byte. The existing code was doing that with a while loop even though the addition should only need to be done once. That logic won't work (will loop forever) if TSC wraps around at the 8th byte. Theoretically that would take at least 10 years, unless something else went wrong. And what else could go wrong. Well, if the chunks of trace data are processed out of order, it will make it look like the 7-byte TSC has gone backwards (i.e. wrapped). If that happens 256 times then stuck in the while loop it will be. Fix that by getting rid of the unnecessary while loop. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/r/1443186956-18718-4-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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