diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-02-01 22:59:22 -0800 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-02-03 14:35:51 -0800 |
| commit | 961140fab379408c7cfb74b139c56d092d4e0810 (patch) | |
| tree | d7effda80b85c609659112fdec9dfba750fe1168 /Documentation/devicetree | |
| parent | 90ef3159f6decd03070bdcc8870be2cd2a6947da (diff) | |
ARM: tegra: Move PWM PMIC binding into DFLL sub-node
Updated definition of DFLL DT binding: moved PWM PMIC integration to
DFLL device sub-node (from root node). Modified DT parsing in CL-DVFS
driver accordingly.
Bug 1442709
Change-Id: I1d3919589ae95c7f3c86c435716577d433c73e4d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/362657
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt index c7e216565d56..2188203dc2dc 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-dfll.txt @@ -32,13 +32,6 @@ Required properties: for this DFLL instance. Optional properties: -- i2c-pmic-integration : phandle pointing to the integration data for - PMIC controlled by this DFLL instance via I2C interface. -- pwm-pmic-integration : phandle pointing to the integration data for - PMIC controlled by this DFLL instance via PWM interface. -Note that one and only one of 'i2c-pmic-integration', or 'pwm-pmic-integration', -must be specified. - - i2c-quiet-output-workaround : If the DFLL IP block version implemented on this SoC requires the I2C output to the PMIC to be quiesced before disabling it, this property should be set. @@ -52,6 +45,16 @@ must be specified. - status : device availability -- managed by the DT integration code. Should be set to "okay" if the DFLL is to be used on this board type. +- i2c-pmic-integration : phandle pointing to the integration data for + PMIC controlled by this DFLL instance via I2C interface. + +Optional subnode: +- pwm-pmic-integration : should have integration data for PMIC controlled by + this DFLL instance via PWM interface. + +Note that one and only one of 'i2c-pmic-integration', or 'pwm-pmic-integration', +must be included. + Example: dfll@70110000 { @@ -126,7 +129,7 @@ cpu_dfll_pmic_integration { pmic-undershoot-gb = <100>; }; -DFLL PWM PMIC integration node in the board DTS file +DFLL PWM PMIC integration subnode in the board DTS file Required properties: - compatible : Must be @@ -157,13 +160,17 @@ or 'pwm-2wire' must be specified. Example: -pwm_dfll: cpu_dfll_pmic_integration { - compatible = "nvidia,tegra124-dfll-pwm"; - pwm-1wire-buffer; - pwm-data-gpio = <&gpio TEGRA_GPIO(X, 0) 0>; - pwm-buffer-ctrl-gpio = <&gpio TEGRA_GPIO(S, 5) 1>; - #pwm-cells = <2>; - pwm-regulator = <&cpu_pwm_reg>; +dfll@70110000 { + board-params = <&{/cpu_dfll_board_params}>; + status = "okay"; + pwm_dfll: pwm-pmic-integration { + compatible = "nvidia,tegra124-dfll-pwm"; + pwm-1wire-buffer; + pwm-data-gpio = <&gpio TEGRA_GPIO(X, 0) 0>; + pwm-buffer-ctrl-gpio = <&gpio TEGRA_GPIO(S, 5) 1>; + #pwm-cells = <2>; + pwm-regulator = <&cpu_pwm_reg>; + }; }; pwm_regulators { |