diff options
author | Chircu-Mare Bogdan-Petru <Bogdan.Chircu@freescale.com> | 2015-11-03 17:25:46 +0200 |
---|---|---|
committer | Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> | 2019-11-29 11:43:04 +0200 |
commit | f53e570ff0d796f523c6246c2ce5faa13091431a (patch) | |
tree | 8191e9e4a53ab8421e5338e7ea812b1f731ecade | |
parent | 58b9c9e00e30deb2a8a2f379134432914a5f14cf (diff) |
arm64: dts: s32v234: Add FlexCAN nodes for EVB and SBC
S32V234 SoCs provide two instances of FlexCAN. Each of S32V234-EVB and
S32V234-SBC use both of them. Add the can nodes and the necessary
pinctrl groups for FlexCAN PAD configurations in SIUL2.
The pinctrl_can* nodes for SBC include a fix for an S-pin reliability
issue.
Signed-off-by: Chircu-Mare Bogdan-Petru <Bogdan.Chircu@freescale.com>
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Kay Potthoff <Kay.Potthoff@microsys.de>
Signed-off-by: Costin Carabas <costin.carabas@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
-rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234-evb.dts | 28 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234-sbc.dts | 46 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234.dtsi | 22 |
3 files changed, 96 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts index 8439b7e3a450..d26845a39de8 100644 --- a/arch/arm64/boot/dts/freescale/s32v234-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts @@ -16,6 +16,18 @@ }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + &siul2 { status = "okay"; s32v234-evb { @@ -25,6 +37,22 @@ * Manual states. */ + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + >; + }; + pinctrl_uart0: uart0grp { fsl,pins = < S32V234_PAD_PA12__UART0_TXD diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts index aba08280e2da..a481a1969928 100644 --- a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts +++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts @@ -22,6 +22,18 @@ }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -47,6 +59,40 @@ * Manual states. */ + pinctrl_can0: can0grp { + fsl,pins = < + S32V234_PAD_PA2__CAN_FD0_TXD + S32V234_PAD_PA3__CAN_FD0_RXD_OUT + S32V234_PAD_PA3__CAN_FD0_RXD_IN + /* + * Configure pin C12 as GPIO[6] in MSCR#6. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.75V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + S32V234_PAD_PA4__CAN_FD1_TXD + S32V234_PAD_PA5__CAN_FD1_RXD_OUT + S32V234_PAD_PA5__CAN_FD1_RXD_IN + /* + * Configure pin C11 as GPIO[7] in MSCR#7. + * Effect: the S-pin at CAN is not longer + * flowting at ~0.39V, but driven to low ~0.0V. + */ + S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \ + | PAD_CTL_OBE \ + | PAD_CTL_DSE_34 \ + | PAD_CTL_PUS_33K_UP) + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < S32V234_PAD_PC13__MDC diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 06525ed51b64..47db198b36ad 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -17,6 +17,8 @@ #size-cells = <2>; aliases { + can0 = &can0; + can1 = &can1; serial0 = &uart0; serial1 = &uart1; }; @@ -186,6 +188,16 @@ status = "disabled"; }; + can0: flexcan@40055000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x40055000 0x0 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + usdhc0: usdhc@4005d000 { compatible = "fsl,s32v234-usdhc"; reg = <0x0 0x4005D000 0x0 0x1000>; @@ -227,6 +239,16 @@ clock-names = "lin"; status = "disabled"; }; + + can1: flexcan@400be000 { + compatible = "fsl,s32v234-flexcan"; + reg = <0x0 0x400be000 0x0 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks S32V234_CLK_CAN>, + <&clks S32V234_CLK_CAN>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; }; }; |