diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-10-18 09:40:07 +0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-10-18 08:24:49 +0200 |
| commit | 1140f9ed051011e06a2a15c73efe57ac0b0cdc8d (patch) | |
| tree | 3d0986cafb2122501e45488ab955bce73412d5f1 | |
| parent | bfd02b3c557caa083be0d55a3164ede706a446e1 (diff) | |
drm/i915/gvt: Fix build failure after intel_engine_cs change
Change GVT-g code reference for intel_engine_cs from static array to
allocated pointer after commit 3b3f1650b1ca ("drm/i915: Allocate
intel_engine_cs structure only for the enabled engines").
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161018014007.29369-1-zhenyuw@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/execlist.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/scheduler.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 4a00ee7ff020..c50a3d1a5131 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -39,7 +39,7 @@ #define _EL_OFFSET_STATUS_PTR 0x3A0 #define execlist_ring_mmio(gvt, ring_id, offset) \ - (gvt->dev_priv->engine[ring_id].mmio_base + (offset)) + (gvt->dev_priv->engine[ring_id]->mmio_base + (offset)) #define valid_context(ctx) ((ctx)->valid) #define same_context(a, b) (((a)->context_id == (b)->context_id) && \ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index d59a934b6e32..e8ec403b75a1 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -134,7 +134,7 @@ static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) reg &= ~GENMASK(11, 0); for (i = 0; i < I915_NUM_ENGINES; i++) { - if (gvt->dev_priv->engine[i].mmio_base == reg) + if (gvt->dev_priv->engine[i]->mmio_base == reg) return i; } return -1; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 732672b7d22b..b15cdf5978a9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -68,7 +68,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) workload->ctx_desc.lrca); context_page_num = intel_lr_context_size( - &gvt->dev_priv->engine[ring_id]); + gvt->dev_priv->engine[ring_id]); context_page_num = context_page_num >> PAGE_SHIFT; @@ -171,7 +171,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) shadow_ctx->desc_template = workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - workload->req = i915_gem_request_alloc(&dev_priv->engine[ring_id], + workload->req = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR_OR_NULL(workload->req)) { gvt_err("fail to allocate gem request\n"); @@ -298,7 +298,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) workload->ctx_desc.lrca); context_page_num = intel_lr_context_size( - &gvt->dev_priv->engine[ring_id]); + gvt->dev_priv->engine[ring_id]); context_page_num = context_page_num >> PAGE_SHIFT; |