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authorKerwin Wan <kerwinw@nvidia.com>2013-03-28 18:17:16 +0800
committerRiham Haidar <rhaidar@nvidia.com>2013-03-29 20:39:08 -0700
commit599cee8c196fa219ddf408303212a77c7686447c (patch)
treea696eb6780f121e0a916ea0f2c08c896a7525d47
parentb13b0d6c8a6c04d96d5040568e6d1dd3665ef69e (diff)
arm: tegra: macallan: set vdd_rtc to 950mV during lp0
When vdd_rtc is set to 900mv, cpu will meet hard hang after wake up from lp0. Hardware team should do WAT to get the proper margin for vdd_rtc. Set vdd_rtc to 950mV to avoid this issue now. Bug 1262674 Change-Id: Ic3ddfeb586a78e6731178bb6bd672dda0ae49566 Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/213967 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-macallan-power.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-macallan-power.c b/arch/arm/mach-tegra/board-macallan-power.c
index bc32dafa17b2..4b72c33242e4 100644
--- a/arch/arm/mach-tegra/board-macallan-power.c
+++ b/arch/arm/mach-tegra/board-macallan-power.c
@@ -236,7 +236,7 @@ PALMAS_PDATA_INIT(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 0, 0);
PALMAS_PDATA_INIT(ldo5, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0);
PALMAS_PDATA_INIT(ldo6, 2850, 2850, palmas_rails(smps9), 1, 1, 1, 0);
PALMAS_PDATA_INIT(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0);
-PALMAS_PDATA_INIT(ldo8, 900, 900, NULL, 1, 1, 1, 0);
+PALMAS_PDATA_INIT(ldo8, 950, 950, NULL, 1, 1, 1, 0);
PALMAS_PDATA_INIT(ldo9, 1800, 2900, palmas_rails(smps9), 0, 0, 1, 0);
PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 0, 0, 1, 0);
PALMAS_PDATA_INIT(ldousb, 3300, 3300, NULL, 0, 0, 1, 0);