| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
|
|
Fix Coverity CID 5209712: Uninitialized scalar variable (UNINIT)
issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
refact the dram low power related code to make it more
friendly for different dram config or different board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Add FSL_SIP_MISC_SET_TEMP support for setting thermal
alarm function.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
add LPDDR4 DVFS support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Add SIP service for OTP reading/writing for use
in u-boot
Signed-off-by: Teo Hall <teo.hall@nxp.com>
|
|
SC_R_IRQSTR_SCU2 can be OFF in system suspend if there
is no wakeup irq enabled from non-secure OS partion.
Add wakeup source check to decide if turning off
SC_R_IRQSTR_SCU2 or NOT when suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
i.MX8MM is a new soc of the i.MX8M family, this patch
add the basic support for i.MX8MM. further code optimization
needed. WAIT mode support is currently disabled, will be enabled
later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
clean up the license identifier with short SPDX short identifier.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Export build info for all i.mx8
Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
|
On i.MX8MQ, NOC may need different settings for different
use cases, so add SIP for NOC settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Since the HAB only works in secure mode. The BL33 runs at EL2 non-secure can't
intialize the HAB successfully. So add the SIP call for these HAB interfaces,
BL33 will trap to ATF to run the HAB.
The HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to
authenticate image. Add these relevant memory region to MMU. Also extend the
stack size of each core to avoid stack overflow by HAB.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add watchdog pretimeout/status interfaces to sync with scfw.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
|
|
i.MX8MQ does NOT update revision info in ANATOP_DIGPROG
register, so the revision info needs to read from ROM,
for security reason, this needs to be done in ATF, so
add this SIP support for kernel.
The A0 chip's ROM version is located at 0x800, and B0
chip is located at 0x83c.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Add src sip to handle M4 boot and status check
Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
|
When changing the DDR frequency, the DDRC will block
AXI access, so the code for changing the frequency need
to be run on OCRAM not make sure no DDR access at this stage.
the DDR frequency change request is from EL1 linux kernel side,
we use the SiP service call to trap the DDR frequency change operation
from linux kernel to ATF.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
|
|
Add a new SIP call FSL_SIP_BUILDINFO to return the current commit id
in 7 hexadecimal digits which are parsed from the version_string.
Signed-off-by: Ye Li <ye.li@nxp.com>
|
|
Add SRTC SIP support for i.MX8QM/i.MX8QXP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Linux kernel will issue cpu-freq scale via SIP, ATF
calls SCFW API to finish the CPU frequency scale.
Move SIP service code from i.mx8mq to common place for
all i.mx SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
