Age | Commit message (Collapse) | Author |
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setup
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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fix Coverity: CID 5243766: Uninitialized scalar variable (UNINIT)
issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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If no valid dram info to copy from DRAM, skip
copy the dram info.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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refact the dram low power related code to make it more
friendly for different dram config or different board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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The RFSHCTL3.refresh_mode should be set normal mode if we
want to disable auto refresh mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Update the DDR4 DVFS flow
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add ddr4 retention flow for imx8m.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Read the mode register setting from the DDRC, then we can
make the DVFS flow more indepent from the actual DDR config.
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is
being used by u-boot. This is why u-boot crashes.
Changing the peripherals to protect, instead of gpio4 and 5, use csu
and rdc registers instead.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
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imx_v2018.03 u-boot uses ROM's APIs: check_target and failsafe. So for iMX8M
platforms, we have to implement the sip calls and use ATF to call them when
u-boot running at non-secure world.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The DRAM APB bus clock rate is wrong before and after DVFS.
The register offset for APB bus clock is wrong, so fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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add LPDDR4 DVFS support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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All the DRAM timing related config is saved by SPL in OCRAM_S,
so no need to do save for these configs in ATF anymore.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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skip init the dram info if the ddr type is DDR4,
support for it will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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re-design the dram power management code to make it more
common for all i.MX8M SOCs. code need to refact and optimize
to make more better. Using this common code on i.MX8MM first,
for i.MX8MQ, will move to this later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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As the i.MX8MM and i.MX8MQ share the same hab file, move it
to common/imx8m, make it reusable for all i.MX8M SOCs.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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