diff options
| -rw-r--r-- | plat/imx/imx8m/ddr/ddr4_dvfs.c | 17 | ||||
| -rw-r--r-- | plat/imx/imx8m/ddr/dram.c | 13 |
2 files changed, 24 insertions, 6 deletions
diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index 86347928..72899452 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -9,7 +9,8 @@ #include <dram.h> -void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank) +void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, + uint32_t rank, uint32_t dram_type) { uint32_t val, mr_mirror, data_mirror; @@ -27,9 +28,14 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank) val = mmio_read_32(DDRC_DIMMCTL(0)); if ((val & 0x2) && (rank == 0x2)) { mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1); /* BA0, BA1 swap */ - data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | + if (dram_type == DDRC_DDR4) + data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | - ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; + ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; + else + data_mirror = (data & 0xfe07) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | + ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | + ((data & 0x100)>>1); } else { mr_mirror = mr; data_mirror = data; @@ -54,6 +60,7 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank) void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) { uint32_t num_rank = info->num_rank; + uint32_t dram_type = info->dram_type; /* * 15. Perform MRS commands as required to re-program * timing registers in the SDRAM for the new frequency @@ -62,9 +69,9 @@ void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) for (int i = 1; i <= num_rank; i++) { for (int j = 0; j < 6; j++) - ddr4_mr_write(j, info->mr_table[pstate][j], 0, i); + ddr4_mr_write(j, info->mr_table[pstate][j], 0, i, dram_type); - ddr4_mr_write(6, info->mr_table[pstate][7], 0, i); + ddr4_mr_write(6, info->mr_table[pstate][7], 0, i, dram_type); } } diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c index 49385909..b886b931 100644 --- a/plat/imx/imx8m/ddr/dram.c +++ b/plat/imx/imx8m/ddr/dram.c @@ -189,6 +189,17 @@ void dram_info_init(unsigned long dram_timing_base) rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags); if (rc) panic(); + + if (dram_info.dram_type == DDRC_LPDDR4 && current_fsp != 0x0) { + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + lpddr4_swffc(&dram_info, dev_fsp, 0x0); + dev_fsp = (~dev_fsp) & 0x1; + } else if (current_fsp != 0x0) { + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + ddr4_swffc(&dram_info, 0x0); + } } @@ -272,7 +283,7 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle, if (dram_info.dram_type == DDRC_LPDDR4) { lpddr4_swffc(&dram_info, dev_fsp, fsp_index); dev_fsp = (~dev_fsp) & 0x1; - } else if (dram_info.dram_type == DDRC_DDR4) { + } else { ddr4_swffc(&dram_info, fsp_index); } |