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-rw-r--r--plat/nvidia/tegra/soc/t186/plat_psci_handlers.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index e91d82fb..1a77c5bf 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -139,6 +139,7 @@ int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
cpu_context_t *ctx = cm_get_context(NON_SECURE);
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
+ int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
assert(ctx);
assert(gp_regs);
@@ -150,6 +151,10 @@ int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7,
0, TEGRA_ARI_SYSTEM_SC7);
+ /* Disable Denver's DCO operations */
+ if (impl == DENVER_IMPL)
+ denver_disable_dco();
+
/* Turn off CPU */
return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE, 0);