diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-01-18 13:47:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-01-18 13:47:06 +0000 |
| commit | f38d93fdbf82ebec321c70f7bc15fe12b7d57275 (patch) | |
| tree | d337e65bf50c885e0d69b78de8f15d9a8f6baa38 /plat/rockchip/common | |
| parent | faaa9453cf9d74fe2611ed04692381d967387657 (diff) | |
| parent | 7a2b35d807960d9f0206d04b2800176ec995a690 (diff) | |
Merge pull request #801 from masahir0y/cleanup
Macro cleanups
Diffstat (limited to 'plat/rockchip/common')
| -rw-r--r-- | plat/rockchip/common/bl31_plat_setup.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index b073bde2..66678d36 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -46,9 +46,6 @@ unsigned long __RO_START__; unsigned long __RO_END__; -unsigned long __COHERENT_RAM_START__; -unsigned long __COHERENT_RAM_END__; - /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be @@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__; #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -/* - * The next 2 constants identify the extents of the coherent memory region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols - * refer to page-aligned addresses. - */ -#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void) plat_cci_init(); plat_cci_enable(); plat_configure_mmu_el3(BL31_RO_BASE, - (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL_COHERENT_RAM_END - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, - BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT); + BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END); } |