diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2015-07-27 13:00:50 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2015-07-27 17:34:41 +0530 |
| commit | 42ca2d86c8ef3cc7b44db65343f2275177fe9ff3 (patch) | |
| tree | 8526217c840d3a19f4856346eb2b27b29ac6eabe /plat/nvidia/tegra/include | |
| parent | fcee3b00ba41be71f801e58f13ad7673c0e61bcf (diff) | |
Tegra210: enable WRAP to INCR burst type conversions
The Memory Select Switch Controller routes any CPU transactions to
the appropriate slave depending on the transaction address. During
system suspend, it loses all config settings and hence the CPU has
to restore them during resume.
This patch restores the controller's settings for enabling WRAP to
INCR burst type conversions on the master ports, for any incoming
requests from the AXI slave ports.
Tested by performing multiple system suspend cycles.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include')
| -rw-r--r-- | plat/nvidia/tegra/include/t210/tegra_def.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index a54de5a1..750e6e3f 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -68,6 +68,23 @@ #define TEGRA_GICC_BASE 0x50042000 /******************************************************************************* + * Tegra Memory Select Switch Controller constants + ******************************************************************************/ +#define TEGRA_MSELECT_BASE 0x50060000 + +#define MSELECT_CONFIG 0x0 +#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) +#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) +#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) +#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) +#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) +#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ + UNSUPPORTED_TX_ERR_MASTER1_BIT) +#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ + ENABLE_WRAP_INCR_MASTER1_BIT | \ + ENABLE_WRAP_INCR_MASTER0_BIT) + +/******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ #define TEGRA_TMRUS_BASE 0x60005010 |