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| author | danh-arm <dan.handley@arm.com> | 2015-06-18 14:58:33 +0100 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2015-06-18 14:58:33 +0100 |
| commit | 09aa0392b3a632ccf0dcbaaa5918a8aea4288551 (patch) | |
| tree | c7ae5f4e62b72c3ef0bccfd9d5f658c1f471fd4e /plat/nvidia/tegra/include | |
| parent | 79b1ebdaae021c0a9c4880849d181a5b91ecac8a (diff) | |
| parent | 9a9645105b7aece52f4fdefc7fdeec7d73ceaed5 (diff) | |
Merge pull request #319 from vwadekar/tegra-video-mem-aperture-v3
Reserve a Video Memory aperture in DRAM memory
Diffstat (limited to 'plat/nvidia/tegra/include')
| -rw-r--r-- | plat/nvidia/tegra/include/drivers/memctrl.h | 5 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/tegra_private.h | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index 867f09ef..26c80576 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -64,6 +64,10 @@ #define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG1_0 0x74 +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + static inline uint32_t tegra_mc_read_32(uint32_t off) { return mmio_read_32(TEGRA_MC_BASE + off); @@ -76,5 +80,6 @@ static inline void tegra_mc_write_32(uint32_t off, uint32_t val) void tegra_memctrl_setup(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); #endif /* __MEMCTRL_H__ */ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 484879e2..fa29fbb4 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -34,6 +34,12 @@ #include <xlat_tables.h> #include <platform_def.h> +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE 0x80000000 +#define TEGRA_DRAM_END 0x27FFFFFFF + typedef struct plat_params_from_bl2 { uint64_t tzdram_size; uintptr_t bl32_params; @@ -66,5 +72,6 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr); /* Declarations for tegra_bl31_setup.c */ plat_params_from_bl2_t *bl31_get_plat_params(void); +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); #endif /* __TEGRA_PRIVATE_H__ */ |