diff options
author | davidcunado-arm <david.cunado@arm.com> | 2017-03-17 13:31:05 +0000 |
---|---|---|
committer | GitHub <noreply@github.com> | 2017-03-17 13:31:05 +0000 |
commit | effe0dcab170a524dffde76dd88c582814c6b8a9 (patch) | |
tree | ec8ee83d6081b867c4daa63259712459cc1d355f /drivers | |
parent | 510a9de79fe14460ec591bba4aa8790665c3f86a (diff) | |
parent | 311b1773641674e4b498dbf577635d0c4c63ab48 (diff) |
Merge pull request #858 from soby-mathew/sm/gic_driver_data_fix
Flush the GIC driver data after init
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/arm/gic/v2/gicv2_main.c | 13 | ||||
-rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 14 |
2 files changed, 25 insertions, 2 deletions
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 305a8b07..fcc4b8b7 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -158,6 +158,17 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) driver_data = plat_driver_data; + /* + * The GIC driver data is initialized by the primary CPU with caches + * enabled. When the secondary CPU boots up, it initializes the + * GICC/GICR interface with the caches disabled. Hence flush the + * driver_data to ensure coherency. This is not required if the + * platform has HW_ASSISTED_COHERENCY enabled. + */ +#if !HW_ASSISTED_COHERENCY + flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); + flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); +#endif INFO("ARM GICv2 driver initialized\n"); } diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 5abaa1ce..2efab4c8 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -116,6 +116,18 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) driver_data = plat_driver_data; + /* + * The GIC driver data is initialized by the primary CPU with caches + * enabled. When the secondary CPU boots up, it initializes the + * GICC/GICR interface with the caches disabled. Hence flush the + * driver_data to ensure coherency. This is not required if the + * platform has HW_ASSISTED_COHERENCY enabled. + */ +#if !HW_ASSISTED_COHERENCY + flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); + flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); +#endif + INFO("GICv3 %s legacy support detected." " ARM GICV3 driver initialized in EL3\n", gicv2_compat ? "with" : "without"); |