diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2018-07-05 13:37:11 +0800 |
---|---|---|
committer | Anson Huang <Anson.Huang@nxp.com> | 2018-07-05 13:37:11 +0800 |
commit | b9355f548ba6f1d969c4ad9c4b4a0c71f94c43db (patch) | |
tree | 6bda4e04a6c8a12ce82334305bd1595e47461d43 | |
parent | 835c73b20e3d1d2bf6cbdb9e5495521dae8eb0ab (diff) |
imx8mq/imx8mm: switch to MULTI_CONSOLE_API for debug uart support
Switch to MULTI_CONSOLE_API to make debug UART work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
-rw-r--r-- | plat/imx/common/include/uart.h | 138 | ||||
-rw-r--r-- | plat/imx/common/mxcuart_console.S | 262 | ||||
-rw-r--r-- | plat/imx/imx8mm/imx8mm_bl31_setup.c | 9 | ||||
-rw-r--r-- | plat/imx/imx8mq/imx8mq_bl31_setup.c | 8 |
4 files changed, 198 insertions, 219 deletions
diff --git a/plat/imx/common/include/uart.h b/plat/imx/common/include/uart.h new file mode 100644 index 00000000..f016f21e --- /dev/null +++ b/plat/imx/common/include/uart.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __IMX_UART_H__ +#define __IMX_UART_H__ + +#include <console.h> + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define URXD_RX_DATA (0xFF) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + +#ifndef __ASSEMBLY__ + +#include <types.h> + +typedef struct { + console_t console; + uintptr_t base; +} console_uart_t; + +int console_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, + console_uart_t *console); +#endif /*__ASSEMBLY__*/ + +#endif /* __IMX_UART_H__*/ diff --git a/plat/imx/common/mxcuart_console.S b/plat/imx/common/mxcuart_console.S index d84e4fd8..2f78c416 100644 --- a/plat/imx/common/mxcuart_console.S +++ b/plat/imx/common/mxcuart_console.S @@ -4,227 +4,65 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <arch.h> #include <asm_macros.S> - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define URXD_RX_DATA (0xFF) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ -#define UCR1 0x80 /* Control Register 1 */ -#define UCR2 0x84 /* Control Register 2 */ -#define UCR3 0x88 /* Control Register 3 */ -#define UCR4 0x8c /* Control Register 4 */ -#define UFCR 0x90 /* FIFO Control Register */ -#define USR1 0x94 /* Status Register 1 */ -#define USR2 0x98 /* Status Register 2 */ -#define UESC 0x9c /* Escape Character Register */ -#define UTIM 0xa0 /* Escape Timer Register */ -#define UBIR 0xa4 /* BRM Incremental Register */ -#define UBMR 0xa8 /* BRM Modulator Register */ -#define UBRC 0xac /* Baud Rate Count Register */ -#define UTS 0xb4 /* UART Test Register (mx31) */ - -#define TXTL 2 /* reset default */ -#define RXTL 1 /* reset default */ -#define RFDIV 4 /* divide input clock by 2 */ - - .globl console_core_init - .globl console_core_putc - .globl console_core_getc - .globl console_core_flush - -/* console_core_init */ -func console_core_init - mov w0, wzr +#include <console_macros.S> +#include <assert_macros.S> +#include "uart.h" + + .globl console_uart_register + .globl console_uart_init + .globl console_uart_putc + .globl console_uart_getc + +func console_uart_register + mov x7, x30 + mov x6, x3 + cbz x6, register_fail + str x0, [x6, #CONSOLE_T_DRVDATA] + + bl console_uart_init + cbz x0, register_fail + + mov x0, x6 + mov x30, x7 + finish_console_register uart + +register_fail: + ret x7 +endfunc console_uart_register + +func console_uart_init + mov w0, #1 ret - /* Check the input base address */ - cbz x0, init_fail - /* Check baud rate and uart clock for sanity */ - cbz w1, init_fail - cbz w2, init_fail - - /* clear UCR1 and UCR2 */ - str wzr, [x0, #UCR1] - str wzr, [x0, #UCR2] - - /* Check SRST bit of UCR2 */ - - /* Set UCR3 and UCR4 */ - mov w3, #0x0704 - orr w3, w3, #UCR3_ADNIMP - str w3, [x0, #UCR3] - - mov w3, #0x8000 - str w3, [x0, #UCR4] - - mov w3, #0x2b - str w3, [x0, #UESC] - - str wzr, [x0, #UTIM] - str wzr, [x0, #UTS] - - /* Set baud rate */ - mov w4, #RFDIV - lsl w3, w4, #UFCR_RFDIV_SHF - mov w4, #TXTL - orr w3, w3, w4, lsl #UFCR_TXTL_SHF - mov w4, #RXTL - orr w3, w3, w4, lsl #UFCR_RXTL_SHF - str w3, [x0, #UFCR] - - mov w3, #0xF - str w3, [x0, #UBIR] - - lsl w3, w2, #1 - udiv w3, w1, w3 - str w3, [x0, #UBMR] +endfunc console_uart_init - /* Configure the UCR2 and UCR1 */ - mov w3, #UCR2_WS - orr w3, w3, #UCR2_IRTS - orr w3, w3, #UCR2_RXEN - orr w3, w3, #UCR2_TXEN - orr w3, w3, #UCR2_SRST - str w3, [x0, #UCR2] +func console_uart_putc + ldr x1, [x1, #CONSOLE_T_DRVDATA] + cbz x1, putc_error - mov w3, #UCR1_UARTEN - str w3, [x0, #UCR1] -init_fail: - ret -endfunc console_core_init - - /* -------------------------------------------------------- - * int console_core_putc(int c, unsigned int base_addr) - * Function to output a character over the console. It - * returns the character printed on success or -1 on error. - * In : w0 - character to be printed - * x1 - console base address - * Out : return -1 on error else return character. - * Clobber list : x2 - * -------------------------------------------------------- - */ -func console_core_putc - /* Check the input parameter */ - cbz w1, putc_error - - str w0, [x1, #UTXD] + /* Prepare '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f 1: + /* Check if the transmit FIFO is full */ ldr w2, [x1, #UTS] tbz w2, #6, 1b - - cmp w0, #0xA - b.ne 2f - mov w0, #0xD - b console_core_putc + mov w2, #0xD + str w2, [x1, #UTXD] 2: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #UTS] + tbz w2, #6, 2b + str w0, [x1, #UTXD] ret putc_error: mov w0, #-1 ret -endfunc console_core_putc +endfunc console_uart_putc - /* --------------------------------------------- - * int console_core_getc(unsigned int base_addr) - * Function to get a character from the console. - * It returns the character grabbed on success - * or -1 on error. - * In : x0 - console base address - * Out : return -1 on error else return character. - * Clobber list : x0, x1, x2 - * --------------------------------------------- - */ -func console_core_getc +func console_uart_getc + ldr x0, [x0, #CONSOLE_T_DRVDATA] cbz x0, getc_error 1: ldr w1, [x0, #UTS] @@ -237,10 +75,4 @@ func console_core_getc getc_error: mov w0, #-1 ret -endfunc console_core_getc - -/* console_core_flush */ -func console_core_flush - mov w0, wzr - ret -endfunc console_core_flush +endfunc console_uart_getc diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c index 036a83d7..383cf3ac 100644 --- a/plat/imx/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c @@ -22,6 +22,7 @@ #include <tzc380.h> #include <imx_csu.h> #include <imx_rdc.h> +#include <uart.h> /* linker defined symbols */ extern unsigned long __RO_START__; @@ -191,6 +192,10 @@ static void imx8mm_aips_config(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { +#if DEBUG_CONSOLE + static console_uart_t console; +#endif + #if !defined (CSU_RDC_TEST) int i; /* enable CSU NS access permission */ @@ -205,8 +210,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, imx8mm_caam_config(); #if DEBUG_CONSOLE - console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, - IMX_CONSOLE_BAUDRATE); + console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); #endif /* diff --git a/plat/imx/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8mq/imx8mq_bl31_setup.c index 5bea5c0f..5f7d1445 100644 --- a/plat/imx/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8mq/imx8mq_bl31_setup.c @@ -22,6 +22,7 @@ #include <tzc380.h> #include <imx_csu.h> #include <imx_rdc.h> +#include <uart.h> /* linker defined symbols */ #if USE_COHERENT_MEM @@ -126,6 +127,9 @@ void bl31_tzc380_setup(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { +#if DEBUG_CONSOLE + static console_uart_t console; +#endif uint32_t sm_cmd; #if !defined (CSU_RDC_TEST) int i; @@ -184,8 +188,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(0x32df0050, 0x0); #if DEBUG_CONSOLE - console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, - IMX_CONSOLE_BAUDRATE); + console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); #endif /* enable the system counter */ system_counter_init(); |