diff options
author | Naga Sureshkumar Relli <nagasure@xilinx.com> | 2016-07-01 12:52:41 +0530 |
---|---|---|
committer | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2016-07-12 08:05:10 -0700 |
commit | 84629f2f2cf73b6d6180fc8a234f1ea9d423b280 (patch) | |
tree | b5954e86836a4a2ec51a0840c2e244740bb70c71 | |
parent | 6f511c4782f079c75928a4dae3a4e3e4f6754831 (diff) |
bl31: Add error reporting registers
This patch adds cpumerrsr_el1 and l2merrsr_el1 to the register dump on
error for applicable CPUs.
These registers hold the ECC errors on L1 and L2 caches.
This patch updates the A53, A57, A72, A73 (l2merrsr_el1 only) CPU libraries.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a53.h | 10 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 10 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a72.h | 10 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a73.h | 5 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 4 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 4 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a72.S | 4 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a73.S | 3 |
8 files changed, 46 insertions, 4 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 169d8f4b..6976b809 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -57,6 +57,11 @@ #define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -79,4 +84,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index ac4ae570..c5a218b7 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -57,6 +57,11 @@ #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -90,4 +95,9 @@ #define L2ECTLR_RET_CTRL_SHIFT 0 #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index fa10ca90..01edf43b 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -45,6 +45,11 @@ #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ @@ -65,4 +70,9 @@ #define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 2ad04677..13e114a3 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h @@ -41,4 +41,9 @@ #define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A73_H__ */ diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index bb565162..ed546e7e 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -234,11 +234,13 @@ endfunc cortex_a53_cluster_pwr_dwn */ .section .rodata.cortex_a53_regs, "aS" cortex_a53_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" func cortex_a53_cpu_reg_dump adr x6, cortex_a53_regs mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 ret endfunc cortex_a53_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 60929a05..d6b181d0 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -477,11 +477,13 @@ endfunc cortex_a57_cluster_pwr_dwn */ .section .rodata.cortex_a57_regs, "aS" cortex_a57_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" func cortex_a57_cpu_reg_dump adr x6, cortex_a57_regs mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 ret endfunc cortex_a57_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index eb37f2ca..9f04fb72 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -231,11 +231,13 @@ endfunc cortex_a72_cluster_pwr_dwn */ .section .rodata.cortex_a72_regs, "aS" cortex_a72_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" func cortex_a72_cpu_reg_dump adr x6, cortex_a72_regs mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 ret endfunc cortex_a72_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index 70b4c6a5..e1615dbd 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S @@ -144,11 +144,12 @@ endfunc cortex_a73_cluster_pwr_dwn */ .section .rodata.cortex_a73_regs, "aS" cortex_a73_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" + .asciz "cpuectlr_el1", "l2merrsr_el1", "" func cortex_a73_cpu_reg_dump adr x6, cortex_a73_regs mrs x8, CORTEX_A73_CPUECTLR_EL1 + mrs x9, CORTEX_A73_L2MERRSR_EL1 ret endfunc cortex_a73_cpu_reg_dump |