diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/kinetis/twr_k70f120m')
16 files changed, 1722 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog new file mode 100644 index 0000000..1d90bda --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog @@ -0,0 +1,110 @@ +2013-04-09 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + + Add requirement for WRITETHRU data cache startup mode when eDMA is in use. + Sync with change in eDMA driver [ Bugzilla 1001838 ] + +2013-04-09 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k70f120m_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2013-03-09 Ilija Kocho <ilijak@siva.com.mk> + + * misc/redboot_K70_ROM_FPU.ecm: Add ECM file + +2012-11-30 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Sync with variant changes due to + hardware floating point support. Implements CYGINT_HAL_FPV4_SP_D16. + Changed maximum peripheral bus clocks to 75MHz. + [Bugzilla 1001607] + +2012-11-04 Ilija Kocho <ilijak@siva.com.mk> + + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + Recognize 256 Bytes space for virtual vectors in sram. + + * twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + Add settings for Kinetis internal flash. [Bugzilla 1001561] + +2012-09-28 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h + * current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi + * current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h + * current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi + * src/twr_k70f120m_misc.c: + Synchronized with Kinetis variant changes to SDRAM controller support. + Memory layouts adapted to separate data and code cacing partitions. + [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Reference per-package + documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/twr_k70f120m.sgml: + New file -- TWR-K70F120M platform documentation. [Bug 1001580] + +2012-05-17 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + Bug fix: Do not implement external memory interface if Platform startup is + not selected. [ Bugzilla 1001590 ] + +2012-02-25 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi: + * pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h: + * pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi: + * pkgconf/mlt_kinetis_flash_unisram_extram_ram.h: + * pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi: + * pkgconf/mlt_kinetis_flash_unisram_extram_rom.h: + * pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi: + * src/twr_k70f120m_misc.c: + New package -- Freescale TWR-K70F120M board. [Bugzilla 1001579] + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl new file mode 100644 index 0000000..6d469cf --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl @@ -0,0 +1,444 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k70f120m.cdl +## +## Cortex-M Freescale TWR-K70F120M platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2012-02-25 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M { + display "Freescale Kinetis TWR-K70F120M Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k70f120m.h + include_dir cyg/hal + doc ref/kinetis-twr-k70f120m.html + hardware + description " + The Freescale TWR K70F120M Platform HAL package provides the support + needed to run eCos on the TWR K70F120M development system. This package + can also be used for other boards that employ a controller from Kinetis + families." + + compile twr_k70f120m_misc.c + + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { is_active(CYGPKG_DEVS_ETH_FREESCALE_ENET) + implies CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" } + + implements CYGINT_HAL_CACHE + + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU_DEFAULT == "F" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM_DEFAULT == 70 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 30 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM != 50 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == "1M0" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_BLOCK_SIZE == 0x1000 } + requires { is_active(CYGPKG_DEVS_FLASH_KINETIS) implies + CYGNUM_DEVS_KINETIS_FLASH_LONGWORD_SIZE == 8 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART2 + implements CYGINT_IO_FREESCALE_I2C0 + + implements CYGINT_HAL_FREESCALE_UART2 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + implements CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 + implements CYGINT_HAL_CORTEXM_KINETIS_150 + + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX == 75000000 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX == 25000000 } + + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32) } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K70F120M\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYG_HAL_STARTUP_PLF { + display "By platform" + flavor data + parent CYG_HAL_STARTUP_ENV + default_value { "ROM" } + legal_values { "ByVariant" "ROM" "RAM" } + + requires { CYG_HAL_STARTUP_PLF != "ByVariant" implies + CYGPKG_HAL_CORTEXM_KINETIS_DDRMC == 1 } + + description " + Startup tupes provided by the platform, in addition to variant + startup types. + If 'ByVariant' is selected, then startup type shall be selected + from the variant (CYG_HAL_STARTUP_VAR). Platform's 'ROM' startup + builds application similar to Variant's 'ROM' but using external + RAM (DDRAM). 'RAM' startup builds application intended for loading + by RedBoot into external RAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT_PLF { + display "Memory layout by platform" + flavor data + active_if { CYG_HAL_STARTUP_PLF != "ByVariant" } + implements CYGINT_HAL_CORTEXM_KINETIS_DDRAM + no_define + parent CYGHWR_MEMORY_LAYOUT + calculated { + (CYG_HAL_STARTUP_PLF == "ByVariant" ) ? "by variant" : + (CYG_HAL_STARTUP == "RAM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_ram" : + (CYG_HAL_STARTUP == "ROM") ? "kinetis_" + . CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_extram_rom" : + "Error!" + } + description " + Combination of 'Startup type' and 'Kinetis member in use' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_RAM_RESERVED { + display "Reserved RAM space \[Bytes\]" + flavor data + legal_values 0 to 0x40000 + default_value 0x20000 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP { + display "Platform suggested system frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP { + display "Platform suggested auxiliary frequency setpoint" + flavor data + no_define + legal_values 96000000 100000000 120000000 150000000 200000000 + default_value 120000000 + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platgorm XTAL/OSC Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ { + display "Platform XTAL1/OSC1 Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + default_value 50000000 + legal_values { 12000000 50000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC1_CAP { + display "Platform requred XTAL1 || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP == 20 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This option chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console port + if the console and GDB port are the same." + } + + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { + display "ENET MII MDC clock provided by HAL" + flavor data + active_if CYGPKG_DEVS_ETH_FREESCALE_ENET + parent CYGPKG_DEVS_ETH_FREESCALE_ENET + calculated CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS + description " + ENET needs a clock with typical frequency of up to 2.5 MHz for + MII MDC. The input clock, typically provided by HAL, is further + divided by ENET according to setting of ENET MSCR register in order to + provide frequency within 2.5 MHz range." + } + + cdl_option CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT { + display "IEEE 1588 Port" + active_if CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + parent CYGSEM_DEVS_ETH_FREESCALE_ENET_1588 + flavor data + default_value { "B" } + legal_values { "B" "C" "User" } + description " + Digital I/O provided by HAL for ENET IEEE 1588 timers." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + requires { (is_active(CYGSEM_HAL_DCACHE_STARTUP_MODE) + && CYGINT_DEVS_SPI_DSPI_DMA_USE) + implies CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" } + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + legal_values { 0 1 2 3 4 5 } + default_value 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + implements CYGINT_FREESCALE_DSPI1_CS1 + implements CYGINT_FREESCALE_DSPI1_CS2 + implements CYGINT_FREESCALE_DSPI1_CS3 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK70F120M_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml new file mode 100644 index 0000000..6178f5b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/doc/twr_k70f120m.sgml @@ -0,0 +1,165 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k70f120m.sgml --> +<!-- --> +<!-- TWR-K70F120M board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k70f120m"> + <refmeta> + <refentrytitle>TWR-K70F120M Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K70F120M</refname> + <refpurpose>eCos Support for Freescale TWR-K70F120M development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k70f120m-description"><title>Description</title> + <para> + The Freescale TWR-K70F120M is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K70, K60, K10 and K20 + microcontroller subfamilies. K70FN1M0 is a high end member comprising on-chip 1 MiB FLASH + and 128 KiB SRAM memory as well as a 16 KiB unified cache. + K70 parts are equipped with a rich set of communication interfaces including Ethernet USB, UARTs + CAN, SPI and I2C. They also have a Graphics controller and a DMA controller, as well as FlexBus and SDRAM + external memory interfaces. They are mixed signal devices featuring a 16 bit ADC and a 12 bit DAC. + </para> + </refsect1> + <refsect1 id="kinetis-twr-k70f120m-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k70f120m-config-hardware"><title>Hardware Setup</title> + <refsect3 id="kinetis-twr-k70f120m-config-hardware-cpu"><title>TWR-K70F120M setup</title> + <para> + Factory jumper settings on TWR-K70F120M are fitted for standalone operation of the board. + In order to use it with the Ethernet PHY from TWR-SER, some jumpers have to be changed + on both TWR-K70F120M and TWR-SER. Jumper settings for TWR-SER are given in + <link linkend="kinetis-twr-k60n512-config">TWR-K60N512 Configuration</link> and here are the TWR-K70F120M + settings. + </para> + <table frame="all"><title>TWR-K70F120M Jumper setting</title> + <tgroup cols="3" align="center"> + <colspec colnum="1" colname="jumper" colwidth="1*" > + <colspec colnum="2" colname="jumpset" colwidth="1*" > + <colspec colnum="3" colname="desc" colwidth="3*" > + <thead> + <row> + <entry>Jumper</entry> + <entry>Setting</entry> + <entry>Description</entry> + </row> + </thead> + <tbody> + <row> + <entry>J19</entry> + <entry>OFF</entry> + <entry>On board 50MHz oscillator is not powered</entry> + </row> + </tbody> + </tgroup> + </table> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-config-ecos"><title>eCos Configuration</title> + <refsect3 id="twr-k70f120m-clocking"><title>Clocking</title> + <para> + The TWR-K70F120M package defines requirements for the platform clocking. + </para> + </refsect3> + <refsect3 id="twr-k70f120m-memory"><title>Memory</title> + <para> + The K70 has two 64 KiB SRAM banks giving a total of 128KiB on chip SRAM. In addition, on-board there is + 128 MiB of external RAM (SDRAM) and 256 MiB of NAND Flash. + External RAM is divided in two regions: + </para> + <variablelist> + <varlistentry> + <term>ram</term> + <listitem><para> Regular RAM.</para></listitem> + </varlistentry> + <varlistentry> + <term>ramnc</term> + <listitem><para>Non cached RAM. This region contains <literal>.noncache</literal> section.</para></listitem> + </varlistentry> + </variablelist> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-memory"><title>Memory layouts</title> + <para> + Additional platform memory layouts follow the <link linkend="kinetis-var-memory">variant</link> + ones only by putting all RAM sections except <literal>.sram</literal> in the <literal>ram</literal> region. + The linker file names incorporate the segment <filename>_extram_</filename>. + </para> + <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-location"><title>Linker + Script Location</title> + <para> + Linker scripts are found at: + <filename class="directory">hal/kinetis/twr-k70f120m/<version>/include/pkgconf</filename> + </para> + </refsect3> + <refsect3 id="kinetis-twr-k70f120m-memory-ldscript-naming"><title>Linker Script Naming</title> + <para> + Linker script file names have following form: + <filename>mlt_kinetis_<NVM>_<SRAM>_<STARTUP_extram.ldi</filename> + where <filename>PLF</filename> is an optional extension for platform specific scripts and + other segments have meaning as described <link linkend="kinetis-var-table-ldscript-naming">here</link>. + </para> + </refsect3> + </refsect2> + <refsect2 id="kinetis-twr-k70f120m-startup"><title>Startup types</title> + <para> + The platform startup <literal>CYG_HAL_STARTUP_PLF</literal> offers the following startups: + </para> + <variablelist> + <varlistentry> + <term><literal>ROM (Platform)</literal></term> + <listitem><para>Normal startup for stand-alone operation. The eCos image has to be flashed + in internal flash. External RAM is used as main memory. + </para> + <para> + Note: This startup has a name like the one in the variant but generates different images + by invoking a different set of linker scripts. + </para></listitem></varlistentry> + <varlistentry> + <term><literal>RAM (Platform)</literal></term> + <listitem><para>The image is loaded in external RAM by means of RedBoot. + </para></listitem></varlistentry> + <varlistentry> + <term><literal>ByVariant</literal></term> + <listitem><para>Activates the <link linkend="kinetis-var-startup">variant startup types</link>. + </para></listitem></varlistentry> + </variablelist> + </refsect2> + </refsect1> +</refentry> + +<!--</part>--> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h new file mode 100644 index 0000000..80ff30e --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi new file mode 100644 index 0000000..feb1b8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h new file mode 100644 index 0000000..bdfde58 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -0,0 +1,40 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi new file mode 100644 index 0000000..4a09a9b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -0,0 +1,49 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h new file mode 100644 index 0000000..69ba037 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi new file mode 100644 index 0000000..3cd913d --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h new file mode 100644 index 0000000..e0339ca --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi new file mode 100644 index 0000000..694fb95 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -0,0 +1,47 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h new file mode 100644 index 0000000..3e631ed --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-02-15 +// Purpose: TWR-K70F120M platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h new file mode 100644 index 0000000..0d92bd6 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2012-02-25 +// Purpose: TWR-K70F120M platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h new file mode 100644 index 0000000..1329b3c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/plf_io.h @@ -0,0 +1,171 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2012-02-25 +// Purpose: TWR-K70F120M platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> + + +// UART PINs +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +#endif + +#ifndef CYGHWR_HAL_FREESCALE_UART2_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART2_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART2_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_FREESCALE_UART2_PIN_RX +# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_FREESCALE_UART2_PIN_TX +# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_FREESCALE_UART2_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_FREESCALE_UART2_PIN_CTS +#endif + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET0_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + +// DSPI +// DSPI Pins + +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define KINETIS_PIN_SPI1_SCK_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) +#define KINETIS_PIN_SPI1_0_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 1, 7, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 3, 7, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_SCK_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(E, 18, 4, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(E, 19, 4, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm new file mode 100644 index 0000000..d1e3c8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/misc/redboot_K70_ROM_FPU.ecm @@ -0,0 +1,83 @@ +# Redboot minimal configuration +# Target: TWR-K70F120M +# Startup: ROM with external RAM + + +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot Kinetis TWR-K70F120M" ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU { + user_value 1 +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH { + user_value ALL +}; + +cdl_component CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 0 +}; + +#cdl_option CYGBLD_REDBOOT_LOAD_INTO_FLASH { +# user_value 1 +#}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value -1 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value -2 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_ENTRY_COUNT { + user_value 16 +}; + +#cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_BASE { +# user_value 0x20000 +#}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + user_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + user_value ROM +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_component CYGPKG_DEVS_ETH_FREESCALE_ENET_REDBOOT_HOLDS_ESA { + user_value 1 +}; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c new file mode 100644 index 0000000..08500ef --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c @@ -0,0 +1,316 @@ +//========================================================================== +// +// twr_k70f120m_misc.c +// +// Cortex-M4 TWR-K60N512 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2012-02-25 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k70f120m.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +#ifdef CYGHWR_HAL_DDR_SYNC_MODE +#define SYNC_ASYNC 0x3 +#else +#define SYNC_ASYNC 0 +#endif + +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +// DDRAM controller setup parameters +const cyg_uint32 kinetis_ddr_cfg[] = { + 0x00000400, // DDR_CR00 + 0x02000031, // DDR_CR02 + 0x02020506, // DDR_CR03 + 0x06090202, // DDR_CR04 + 0x02020302, // DDR_CR05 + 0x02904002, // DDR_CR06 + 0x01000303, // DDR_CR07 + 0x05030201, // DDR_CR08 + 0x020000c8, // DDR_CR09 + 0x03003207, // DDR_CR10 + 0x01000000, // DDR_CR11 + 0x04920031, // DDR_CR12 + 0x00000005, // DDR_CR13 + 0x00C80002, // DDR_CR14 + 0x00000032, // DDR_CR15 + 0x00000001, // DDR_CR16 + 0x00030300, // DDR_CR20 + 0x00040232, // DDR_CR21 + 0x00000000, // DDR_CR22 + 0x00040302, // DDR_CR23 + 0x0A010201, // DDR_CR25 + 0x0101FFFF, // DDR_CR26 + 0x01010101, // DDR_CR27 + 0x00000003, // DDR_CR28 + 0x00000000, // DDR_CR29 + 0x00000001, // DDR_CR30 + 0x02020101, // DDR_CR34 + 0x01010201, // DDR_CR36 + 0x00000200, // DDR_CR37 + 0x00200000, // DDR_CR38 + 0x01010020, // DDR_CR39 + 0x00002000 | SYNC_ASYNC, // DDR_CR40 + 0x01010020, // DDR_CR41 + 0x00002000 | SYNC_ASYNC, // DDR_CR42 + 0x01010020, // DDR_CR43 + 0x00000000 | SYNC_ASYNC, // DDR_CR44 + 0x03030303, // DDR_CR45 + 0x02006401, // DDR_CR46 + 0x01020202, // DDR_CR47 + 0x01010064, // DDR_CR48 + 0x00020101, // DDR_CR49 + 0x00000064, // DDR_CR50 + 0x02000602, // DDR_CR52 + 0x03c80000, // DDR_CR53 + 0x03c803c8, // DDR_CR54 + 0x03c803c8, // DDR_CR55 + 0x020303c8, // DDR_CR56 + 0x01010002 // DDR_CR57 +}; +#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if !defined(CYG_HAL_STARTUP_RAM) + cyghwr_hal_kinetis_pmc_t *pmc_p = CYGHWR_HAL_KINETIS_PMC_P; + + hal_wdog_disable(); + hal_misc_init(); + + // if ACKISO is set you must clear ackiso before calling pll_init + // or pll init hangs waiting for OSC to initialize + if(pmc_p->regsc & CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M) + pmc_p->regsc |= CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M; + + hal_start_clocks(); +# ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg ); +# endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc1 |= CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M; + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#elif defined CYGMEM_REGION_sram_l + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( ((CYG_ADDRESS)addr >= hal_data_access[i].start) && + ((CYG_ADDRESS)addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_sram_l +# define CASE_CODE 3 +# define CASE_RAMNC 4 + case 2: + *start = (unsigned char *)CYGMEM_REGION_sram_l; + *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); + break; +#else +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; +#endif + +#ifdef CYGMEM_REGION_ramnc + case CASE_RAMNC: + *start = (unsigned char *)CYGMEM_REGION_ramnc; + *end = (unsigned char *)(CYGMEM_REGION_ramnc + CYGMEM_REGION_ramnc_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k70f120m_misc.c |