diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include')
16 files changed, 898 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h new file mode 100644 index 0000000..ac10c73 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/hal_kinetis_flexbus.h @@ -0,0 +1,143 @@ +#ifndef CYGONCE_FLEXBUS_H +#define CYGONCE_FLEXBUS_H +//============================================================================= +// +// flexbus.h +// +// Kinetis FlexBus specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-08-05 +// Purpose: Kinetis FlexBus specific registers +// Description: +// Usage: #include <cyg/hal/flexbus.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//-------------------------------------------------------------------------- +// Flexbus pins + +#define KINETIS_PIN_FB_OPT CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M +#define KINETIS_PIN_FB 5 +#define KINETIS_PIN_FB6 6 + +#define CYGHWR_KINETIS_FB_PIN_AD0 CYGHWR_HAL_KINETIS_PIN(D, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD1 CYGHWR_HAL_KINETIS_PIN(D, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD2 CYGHWR_HAL_KINETIS_PIN(D, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD3 CYGHWR_HAL_KINETIS_PIN(D, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD4 CYGHWR_HAL_KINETIS_PIN(D, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD5 CYGHWR_HAL_KINETIS_PIN(C, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD6 CYGHWR_HAL_KINETIS_PIN(C, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD7 CYGHWR_HAL_KINETIS_PIN(C, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD8 CYGHWR_HAL_KINETIS_PIN(C, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD9 CYGHWR_HAL_KINETIS_PIN(C, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD10 CYGHWR_HAL_KINETIS_PIN(C, 5, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD11 CYGHWR_HAL_KINETIS_PIN(C, 4, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD12 CYGHWR_HAL_KINETIS_PIN(C, 2, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD13 CYGHWR_HAL_KINETIS_PIN(C, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD14 CYGHWR_HAL_KINETIS_PIN(C, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD15 CYGHWR_HAL_KINETIS_PIN(B, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD16 CYGHWR_HAL_KINETIS_PIN(B, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD17 CYGHWR_HAL_KINETIS_PIN(B, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD18 CYGHWR_HAL_KINETIS_PIN(B, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD19 CYGHWR_HAL_KINETIS_PIN(B, 10, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD20 CYGHWR_HAL_KINETIS_PIN(B, 9, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD21 CYGHWR_HAL_KINETIS_PIN(B, 8, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD22 CYGHWR_HAL_KINETIS_PIN(B, 7, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD23 CYGHWR_HAL_KINETIS_PIN(B, 6, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD24 CYGHWR_HAL_KINETIS_PIN(C, 15, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD25 CYGHWR_HAL_KINETIS_PIN(C, 14, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD26 CYGHWR_HAL_KINETIS_PIN(C, 13, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD27 CYGHWR_HAL_KINETIS_PIN(C, 12, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD28 CYGHWR_HAL_KINETIS_PIN(B, 23, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD29 CYGHWR_HAL_KINETIS_PIN(B, 22, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD30 CYGHWR_HAL_KINETIS_PIN(B, 21, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_AD31 CYGHWR_HAL_KINETIS_PIN(B, 20, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_A16 CYGHWR_HAL_KINETIS_PIN(D, 8, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A17 CYGHWR_HAL_KINETIS_PIN(D, 9, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A18 CYGHWR_HAL_KINETIS_PIN(D, 10, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A19 CYGHWR_HAL_KINETIS_PIN(D, 11, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A20 CYGHWR_HAL_KINETIS_PIN(D, 12, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A21 CYGHWR_HAL_KINETIS_PIN(D, 13, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A22 CYGHWR_HAL_KINETIS_PIN(D, 14, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_A23 CYGHWR_HAL_KINETIS_PIN(D, 15, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_CLKOUT CYGHWR_HAL_KINETIS_PIN(C, 3, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CLKOUT_OFF \ + CYGHWR_HAL_KINETIS_PIN(C, 3, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define CYGHWR_KINETIS_FB_PIN_RW CYGHWR_HAL_KINETIS_PIN(C, 11, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_OE CYGHWR_HAL_KINETIS_PIN(B, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +// Following pins are additionally multiplexed by FB_CSPMCR + +#define CYGHWR_KINETIS_FB_PIN_BE23_16 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE31_24 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE15_8 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BE7_0 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_BLS15_8 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS7_0 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS23_16 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_BLS31_24 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_CS5 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS4 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(D, 1, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_CS0_LOW \ + CYGHWR_HAL_KINETIS_PIN(D, 1, CYGHWR_HAL_KINETIS_PORT_PCR_MUX_GPIO, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) + +#define CYGHWR_KINETIS_FB_PIN_TSIZ0 CYGHWR_HAL_KINETIS_PIN(C, 16, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TSIZ1 CYGHWR_HAL_KINETIS_PIN(C, 17, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TST CYGHWR_HAL_KINETIS_PIN(C, 18, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_ALE CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) +#define CYGHWR_KINETIS_FB_PIN_TS CYGHWR_HAL_KINETIS_PIN(D, 0, KINETIS_PIN_FB, KINETIS_PIN_FB_OPT) + +#define CYGHWR_KINETIS_FB_PIN_TA CYGHWR_HAL_KINETIS_PIN(C, 19, KINETIS_PIN_FB6, KINETIS_PIN_FB_OPT) + +//----------------------------------------------------------------------------- +// end of flexbus.h +#endif // CYGONCE_FLEXBUS_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h new file mode 100644 index 0000000..daf0474 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi new file mode 100644 index 0000000..6095daa --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -0,0 +1,41 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h new file mode 100644 index 0000000..a00ce95 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -0,0 +1,40 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram_l (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi new file mode 100644 index 0000000..3888a13 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -0,0 +1,49 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h new file mode 100644 index 0000000..53dceb8 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + + diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi new file mode 100644 index 0000000..f8330ee --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi @@ -0,0 +1,35 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x20000400 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h new file mode 100644 index 0000000..b466a08 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi new file mode 100644 index 0000000..bab581b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -0,0 +1,39 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 + 0x100, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h new file mode 100644 index 0000000..5c6db56 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -0,0 +1,32 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_FBR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_FBR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FBR_CACHED_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE) +#define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE) +#define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi new file mode 100644 index 0000000..b43ce41 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -0,0 +1,47 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_FBR_NON_CACHED_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH configuration field. Must be present at 0x00000400 + // Warning: Omitting FLASH configuration field or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_conf 0x00000400 : { KEEP (*(.flash_conf)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_FBR_CACHED_BASE, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_FBR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h new file mode 100644 index 0000000..5370f8f --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.h @@ -0,0 +1,24 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi new file mode 100644 index 0000000..e74d8a9 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_ram.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA) + USER_SECTION(kinetis_misc, flash, ALIGN (0x8), LMA_EQ_VMA) + + // Kinetis FLASH security configuration. Must be present at 0x00000400 + // Warning: Omitting FLASH security configuration or moving it to + // other location may lock Kinetis controller. + // See src/kinetis_mis.c for definition + + .flash_security 0x00000400 : { KEEP (*(.flash_security)) } > flash + + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) + SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE; diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h new file mode 100644 index 0000000..329056b --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Purpose: TWR-K60N512-FXM platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h new file mode 100644 index 0000000..a443eed --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512-FXM platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h new file mode 100644 index 0000000..6b2ddab --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/plf_io.h @@ -0,0 +1,194 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K60N512 platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k60n512_fxm.h> + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# if 0 +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 5, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 4, 3, 0) +# elif 0 +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# else +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# endif +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# if 0 +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +# endif +#endif + +#if 1 +#ifndef CYGHWR_HAL_FREESCALE_UART4_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART4_PIN_RX CYGHWR_HAL_KINETIS_PIN(E, 25, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART4_PIN_TX CYGHWR_HAL_KINETIS_PIN(E, 24, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + + +# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_FREESCALE_UART4_PIN_RX +# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_FREESCALE_UART4_PIN_TX +# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_FREESCALE_UART4_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_FREESCALE_UART4_PIN_CTS + +#endif +#endif + + +// ENET PINs + +// MDIO +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDIO CYGHWR_HAL_KINETIS_PIN(B, 0, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_MDC CYGHWR_HAL_KINETIS_PIN(B, 1, 4, 0) +// Both RMII and MII interface +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXER CYGHWR_HAL_KINETIS_PIN(A, 5, 4, \ + CYGHWR_HAL_KINETIS_PORT_PCR_PE_M) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD1 CYGHWR_HAL_KINETIS_PIN(A, 12, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_RXD0 CYGHWR_HAL_KINETIS_PIN(A, 13, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXEN CYGHWR_HAL_KINETIS_PIN(A, 15, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD0 CYGHWR_HAL_KINETIS_PIN(A, 16, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_TXD1 CYGHWR_HAL_KINETIS_PIN(A, 17, 4, 0) +// RMII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_RMII0_CRS_DV CYGHWR_HAL_KINETIS_PIN(A, 14, 4, 0) +// MII interface only +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD3 CYGHWR_HAL_KINETIS_PIN(A, 9, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXD2 CYGHWR_HAL_KINETIS_PIN(A, 10, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_RXCLK CYGHWR_HAL_KINETIS_PIN(A, 11, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD2 CYGHWR_HAL_KINETIS_PIN(A, 24, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXCLK CYGHWR_HAL_KINETIS_PIN(A, 25, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_TXD3 CYGHWR_HAL_KINETIS_PIN(A, 26, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_CRS CYGHWR_HAL_KINETIS_PIN(A, 27, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MIIO_TXER CYGHWR_HAL_KINETIS_PIN(A, 28, 4, 0) +#define CYGHWR_IO_FREESCALE_ENET0_PIN_MII0_COL CYGHWR_HAL_KINETIS_PIN(A, 29, 4, 0) +// IEEE 1588 timers +#define CYGHWR_IO_FREESCALE_ENET0_PIN_1588_CLKIN CYGHWR_HAL_KINETIS_PIN(E, 26, 4, 0) + +#if defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_B) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(B, 2, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(B, 3, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(B, 4, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(B, 5, 4, 0) +#elif defined(CYGHWR_HAL_FREESCALE_ENET_E0_1588_PORT_C) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR0 CYGHWR_HAL_KINETIS_PIN(C, 16, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR1 CYGHWR_HAL_KINETIS_PIN(C, 17, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR2 CYGHWR_HAL_KINETIS_PIN(C, 18, 4, 0) +# define CYGHWR_IO_FREESCALE_ENET0_PIN_E0_1588_TMR3 CYGHWR_HAL_KINETIS_PIN(C, 19, 4, 0) +#endif + +// FlexBus Memory +#define CYGHWR_HAL_FB_CSPMCR_G1_SEL CYGHWR_HAL_FB_CSPMCR_G1_TS +#define CYGHWR_HAL_FB_CSPMCR_G2_SEL CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 +#define CYGHWR_HAL_FB_CSPMCR_G3_SEL CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 +#define CYGHWR_HAL_FB_CSPMCR_G4_SEL CYGHWR_HAL_FB_CSPMCR_G4_CS2 +#define CYGHWR_HAL_FB_CSPMCR_G5_SEL CYGHWR_HAL_FB_CSPMCR_G5_TA + +#define CYGHWR_HAL_FB_CSPMCR_SETSEL (CYGHWR_HAL_FB_CSPMCR_G1_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G2_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G3_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G4_SEL + \ + CYGHWR_HAL_FB_CSPMCR_G5_SEL ) + +// DSPI +// DSPI Pins + +#define KINETIS_PIN_SPI1_OUT_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) + +#define KINETIS_PIN_SPI1_CS_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_DSE_M) + +#define KINETIS_PIN_SPI1_IN_OPT (CYGHWR_HAL_KINETIS_PORT_PCR_PE_M | \ + CYGHWR_HAL_KINETIS_PORT_PCR_PS_M) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(D, 9, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(D, 8, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H |