diff options
Diffstat (limited to 'ecos/packages/hal/cortexm/kinetis/twr_k40x256/current')
7 files changed, 934 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog new file mode 100644 index 0000000..21c726c --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/ChangeLog @@ -0,0 +1,72 @@ +2013-04-09 Tomas Frydrych <tomas@sleepfive.com> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_io.h: + Implemented support for I2C [Bugzilla 1001397] + +2013-04-01 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k40x256_misc.c: Clock gating synchronised with variant. + [ Bugzilla 1001814 ] + +2012-11-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + Sync with variant changes due to hardware floating point support. + Changed CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM. [Bugzilla 1001607] + +2012-10-25 Ilija Kocho <ilijak@siva.com.mk> + + * src/twr_k40x256_misc.c: Initialization for separate SRAM regions + synchronized with variant. [Bugzilla 1001606] + +2012-05-19 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: Reference per-package + documentation. + +2012-05-18 Ilija Kocho <ilijak@siva.com.mk> + + * doc/twr_k40x512.sgml: + New file -- TWR-K40X512 platform documentation. [Bug 1001580] + +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_io.h: + * src/twr_k40x256_misc.c: + Add entry for DMA, Add CYG_HAL_STARTUP_ENV. Add DSPI pins for SPI1 bus. + Updated for early clock start. [Bugzilla 1001450] + +2011-08-26 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k40x256.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * src/twr_k40x256_misc.c: + New package -- Freescale TWR-K40X256 board. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl new file mode 100644 index 0000000..2455088 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl @@ -0,0 +1,316 @@ +##========================================================================== +## +## hal_cortexm_kinetis_twr_k40x256.cdl +## +## Cortex-M Freescale TWR-K40X256 platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2011, 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Ilija Kocho <ilijak@siva.com.mk> +## Date: 2011-07-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256 { + display "Freescale Kinetis TWR-K40X256 Platform" + parent CYGPKG_HAL_CORTEXM_KINETIS + define_header hal_cortexm_kinetis_twr_k40x256.h + include_dir cyg/hal + doc ref/kinetis-twr-k40x256.html + hardware + + requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies + (CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 16) } + + requires { CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FPU == "D" } + requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_DEFAULT == "X" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME_DEFAULT == 256 } + requires { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM == "X" + implies CYGHWR_HAL_KINETIS_FLEXRAM_SIZE == 4096 } + + implements CYGINT_IO_SERIAL_FREESCALE_UART3 + implements CYGINT_IO_FREESCALE_I2C0 + implements CYGINT_IO_FREESCALE_I2C1 + + implements CYGINT_HAL_FREESCALE_UART3 + implements CYGINT_HAL_CORTEXM_KINETIS_RTC + + + description " + The Freescale TWR K40X256 Platform HAL package provides + the support needed to run eCos on the TWR K40X256 development + system. This package can also be used for other boards that + employ a controller from Kinetis families." + + compile twr_k40x256_misc.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_kinetis_twr_k40x256.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K40X256\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP_ENV { + display "Startup type" + flavor data + no_define + calculated { + !CYG_HAL_STARTUP_PLF ? CYG_HAL_STARTUP : + ((CYG_HAL_STARTUP_PLF == "ByVariant") ? + (CYG_HAL_STARTUP . "(Variant)") : + (CYG_HAL_STARTUP . "(Platform)")) + } + description " + Startup type configuration defines the system memory layout. + Startup type can be defined by the variant (CYG_HAL_STARTUP_VAR) + or a platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ { + display "Platform Reference Clock Frequency" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + default_value 8000000 + legal_values { 32768 8000000 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_OSC_CAP { + display "Platform requred XTAL || C \[pF\]" + flavor bool + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + requires { CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP == 0 } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLF_RTC { + display "Platform requred RTC XTAL || C \[pF\]" + flavor bool + default_value 0 + parent CYGHWR_HAL_CORTEXM_KINETIS_RTC + requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + legal_values 0 to 2 + default_value 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR board has one serial port fitted to RS232 connector. + This optionchooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The TWR has one serial port fitted to RS232 connector. + This option chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + Note: this should match the value chosen for the console + port if the console and GDB port are the same." + } + + cdl_component CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_BUS { + display "MMC Disk SPI bus" + flavor data + parent CYGPKG_DEVS_DISK_MMC_FREESCALE_DSPI + calculated 1 + + requires CYGHWR_DEVS_SPI_FREESCALE_DSPI1 == 1 + implements CYGINT_DEVS_SPI_FREESCALE_DSPI1 + implements CYGINT_FREESCALE_DSPI1_HAS_MASS + + cdl_option CYGHWR_DEVS_DISK_MMC_FREESCALE_DSPI_CS { + display "Device number (CS)" + flavor data + calculated 0 + implements CYGINT_FREESCALE_DSPI1_CS0 + } + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME { + display "Interrupt priority scheme" + flavor none + description "Consolidated interrupt priority scheme setting." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a + ROM monitor, i.e. applications will be loaded into RAM on the + board, and this ROM monitor may process exceptions or interrupts + generated from the application. This enables features such as + utilizing a separate interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + + cdl_component CYGBLD_HAL_CORTEXM_TWR_MK40X256_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description " + This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml new file mode 100644 index 0000000..e521bca --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/doc/twr_k40x256.sgml @@ -0,0 +1,75 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- {{{ Banner --> + +<!-- =============================================================== --> +<!-- --> +<!-- twr_k40x256.sgml --> +<!-- --> +<!-- TWR-K40X256 board documentation. --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2012 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): Ilija Kocho --> +<!-- Contact(s): ilijak@siva.com.mk --> +<!-- Date: 2012/01/10 --> +<!-- Version: 0.01 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<!-- }}} --> + +<!--<part id="hal-cortexm-kinetis"><title>Freescale Kinetis Family Support</title>--> + +<refentry id="kinetis-twr-k40x256"> + <refmeta> + <refentrytitle>TWR-K40X256-KIT Development kit</refentrytitle> + </refmeta> + <refnamediv> + <refname>CYGPKG_HAL_CORTEXM_KINETIS_TWR_K40X256</refname> + <refpurpose>eCos Support for the Freescale TWR-K40X256 development kit</refpurpose> + </refnamediv> + + <refsect1 id="kinetis-twr-k40x256-description"><title>Description</title> + <para> + The Freescale TWR-K40X256-KIT is a development kit for <link linkend="hal-cortexm-kinetis-var"> + Freescale Kinetis</link> Cortex-M4 based micro-controllers. It covers K40 and K30 microcontroller + subfamilies. K40X256 is a high end member comprising 256 KiB FLASH, 256 KiB FlexMemory and 64 KiB SRAM, + as well as rich set of communication interfaces including USB, UARTs CAN, SPI and I2C. + K40 controllers also feature a Segment LCD controller, a DMA controller and a FlexBus + external memory interface. They are mixed signal devices featuring 16 bit ADC and 12 bit DAC. + </para> + </refsect1> + <refsect1 id="kinetis-twr-k40x256-config"><title>Configuration</title> + <refsect2 id="kinetis-twr-k40x256-config-hardware"><title>Hardware Setup</title> + <para> + No changes to the factory default setup are necessary. + </para> + <refsect3 id="twr-k40x256-clocking"><title>Clocking</title> + <para> + The TWR-K40X256 uses an 8MHz crystal as a clock reference which is stated as a requirement in the platform package. + </para> + </refsect3> + <refsect3 id="twr-k40x256-memory"><title>Memory</title> + <para> K40X245 has two 32KiB SRAM banks giving a total of 64KiB on chip SRAM. </para> + </refsect3> + </refsect2> + </refsect1> +</refentry> + +<!-- </part> --> diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h new file mode 100644 index 0000000..6d35948 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_arch.h @@ -0,0 +1,63 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h new file mode 100644 index 0000000..f23f2e3 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h new file mode 100644 index 0000000..fe85537 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/include/plf_io.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Date: 2011-02-05 +// Purpose: TWR-K40X256 platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> + + +// UART PINs + +#ifndef CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RX CYGHWR_HAL_KINETIS_PIN(C, 16, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_TX CYGHWR_HAL_KINETIS_PIN(C, 17, 3, 0) +# define CYGHWR_HAL_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE +# define CYGHWR_HAL_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_KINETIS_PORT_PIN_NONE + +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_FREESCALE_UART3_PIN_TX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_FREESCALE_UART3_PIN_RTS +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_FREESCALE_UART3_PIN_CTS +#endif + + +// DSPI +// DSPI Pins + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SIN CYGHWR_HAL_KINETIS_PIN(E, 3, 2, KINETIS_PIN_SPI1_IN_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SOUT CYGHWR_HAL_KINETIS_PIN(E, 1, 2, KINETIS_PIN_SPI1_OUT_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_SCK CYGHWR_HAL_KINETIS_PIN(E, 2, 2, KINETIS_PIN_SPI1_OUT_OPT) + +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS0 CYGHWR_HAL_KINETIS_PIN(E, 4, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS1 CYGHWR_HAL_KINETIS_PIN(E, 0, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS2 CYGHWR_HAL_KINETIS_PIN(E, 5, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS3 CYGHWR_HAL_KINETIS_PIN(E, 6, 2, KINETIS_PIN_SPI1_CS_OPT) +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS4 CYGHWR_HAL_KINETIS_PIN_NONE +#define CYGHWR_IO_FREESCALE_SPI1_PIN_CS5 CYGHWR_HAL_KINETIS_PIN_NONE + +// I2C +// I2C Pins + +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SDA CYGHWR_HAL_KINETIS_PIN(B, 2, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C0_PIN_SCL CYGHWR_HAL_KINETIS_PIN(B, 3, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SDA CYGHWR_HAL_KINETIS_PIN(C, 11, 2, 0) +# define CYGHWR_IO_I2C_FREESCALE_I2C1_PIN_SCL CYGHWR_HAL_KINETIS_PIN(C, 10, 2, 0) + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c new file mode 100644 index 0000000..b895c36 --- /dev/null +++ b/ecos/packages/hal/cortexm/kinetis/twr_k40x256/current/src/twr_k40x256_misc.c @@ -0,0 +1,233 @@ +//========================================================================== +// +// twr_k40x256_misc.c +// +// Cortex-M4 TWR-K40X256 EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): ilijak +// Contributor(s): +// Date: 2011-02-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#include <pkgconf/hal_cortexm_kinetis_twr_k40x256.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + +static inline void hal_misc_init(void); + +// DATA and BSS locations +__externC cyg_uint32 __ram_data_start; +__externC cyg_uint32 __ram_data_end; +__externC cyg_uint32 __rom_data_start; +__externC cyg_uint32 __sram_data_start; +__externC cyg_uint32 __sram_data_end; +__externC cyg_uint32 __srom_data_start; +__externC cyg_uint32 __bss_start; +__externC cyg_uint32 __bss_end; + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_system_init( void ) +{ +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) + hal_wdog_disable(); + hal_misc_init(); + hal_start_clocks(); +#endif +} + +//=========================================================================== +// hal_misc_init +//=========================================================================== +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M \ + (CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTA_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTB_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTC_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M) + +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_misc_init(void) +{ + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P; + + // Enable some peripherals' clocks. + sim_p->scgc5 |= CYGHWR_HAL_KINETIS_SIM_SCGC5_PORT_M; + sim_p->scgc6 |= CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M; + + // Disable MPU + mpu_p->cesr = 0; +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct { + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash +#endif +#ifdef CYGMEM_REGION_flexnvm + { CYGMEM_REGION_flexnvm, CYGMEM_REGION_flexnvm+CYGMEM_REGION_flexnvm_SIZE-1 }, // On-chip flexnvm (DFlash) +#endif +#ifdef CYGMEM_REGION_flexram + { CYGMEM_REGION_flexram, CYGMEM_REGION_flexram+CYGMEM_REGION_flexram_SIZE-1 }, // On-chip flexram +#endif +#ifdef CYGMEM_REGION_eeeprom0 + { CYGMEM_REGION_eeeprom0, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom0_SIZE-1 }, // On-chip Enhanced EEPROM +#endif +#ifdef CYGMEM_REGION_eeeprom1 + { CYGMEM_REGION_eeeprom1, CYGMEM_REGION_eeeprom0+CYGMEM_REGION_eeeprom1_SIZE-1 }, // On-chip Enhanced EEPROM +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // Chip specific peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram +#define CASE_CYGMEM_REGION_SRAM 1 + case CASE_CYGMEM_REGION_SRAM: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_SRAM 0 +#endif +#ifdef CYGMEM_REGION_flexram +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM + 1) + case CASE_CYGMEM_REGION_FLEXRAM: + *start = (unsigned char *)CYGMEM_REGION_flexram; + *end = (unsigned char *)(CYGMEM_REGION_flexram + + CYGMEM_REGION_flexram_SIZE); + break; +#else +#define CASE_CYGMEM_REGION_FLEXRAM (CASE_CYGMEM_REGION_SRAM) +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + +//========================================================================== +// EOF twr_k40x256_misc.c |