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/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* Description:
* MPC5125/M54418TWR/Vybrid Nand driver.
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef MPC5125_NFC_H
#define MPC5125_NFC_H
/* Addresses for NFC MAIN RAM BUFFER areas */
#define NFC_MAIN_AREA(n) ((n) * 0x1000)
/* Addresses for NFC SPARE BUFFER areas */
#define NFC_SPARE_BUFFERS 8
#define NFC_SPARE_LEN 0x10
#define NFC_SPARE_AREA(n) (0x800 + ((n) * NFC_SPARE_LEN))
#define PAGE_2K 0x0800
#define PAGE_64 0x0040
/* MPC5125 NFC registers */
/* Typical Flash Commands */
#define READ_PAGE_CMD_CODE 0x7EE0
#define PROGRAM_PAGE_CMD_CODE 0x7FC0
#define ERASE_CMD_CODE 0x4EC0
#define READ_ID_CMD_CODE 0x4804
#define RESET_CMD_CODE 0x4040
#define DMA_PROGRAM_PAGE_CMD_CODE 0xFFC8
#define RANDOM_IN_CMD_CODE 0x7140
#define RANDOM_OUT_CMD_CODE 0x70E0
#define STATUS_READ_CMD_CODE 0x4068
#define PAGE_READ_CMD_BYTE1 0x00
#define PAGE_READ_CMD_BYTE2 0x30
#define PROGRAM_PAGE_CMD_BYTE1 0x80
#define PROGRAM_PAGE_CMD_BYTE2 0x10
#define READ_STATUS_CMD_BYTE 0x70
#define ERASE_CMD_BYTE1 0x60
#define ERASE_CMD_BYTE2 0xD0
#define READ_ID_CMD_BYTE 0x90
#define RESET_CMD_BYTE 0xFF
#define RANDOM_OUT_CMD_BYTE1 0x05
#define RANDOM_OUT_CMD_BYTE2 0xE0
/* NFC ECC mode define */
#define ECC_BYPASS 0x0
#define ECC_8_BYTE 0x1
#define ECC_12_BYTE 0x2
#define ECC_15_BYTE 0x3
#define ECC_23_BYTE 0x4
#define ECC_30_BYTE 0x5
#define ECC_45_BYTE 0x6
#define ECC_60_BYTE 0x7
#define ECC_ERROR 1
#define ECC_RIGHT 0
/***************** Module-Relative Register Offsets *************************/
#define NFC_SRAM_BUFFER 0x0000
#define NFC_FLASH_CMD1 0x3F00
#define NFC_FLASH_CMD2 0x3F04
#define NFC_COL_ADDR 0x3F08
#define NFC_ROW_ADDR 0x3F0c
#define NFC_FLASH_COMMAND_REPEAT 0x3F10
#define NFC_ROW_ADDR_INC 0x3F14
#define NFC_FLASH_STATUS1 0x3F18
#define NFC_FLASH_STATUS2 0x3F1c
#define NFC_DMA1_ADDR 0x3F20
#define NFC_DMA2_ADDR 0x3F34
#define NFC_DMA_CONFIG 0x3F24
#define NFC_CACHE_SWAP 0x3F28
#define NFC_SECTOR_SIZE 0x3F2c
#define NFC_FLASH_CONFIG 0x3F30
#define NFC_IRQ_STATUS 0x3F38
/***************** Module-Relative Register Reset Value *********************/
#define NFC_SRAM_BUFFER_RSTVAL 0x00000000
#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000
#define NFC_FLASH_CMD2_RSTVAL 0x007EE000
#define NFC_COL_ADDR_RSTVAL 0x00000000
#define NFC_ROW_ADDR_RSTVAL 0x11000000
#define NFC_FLASH_COMMAND_REPEAT_RSTVAL 0x00000000
#define NFC_ROW_ADDR_INC_RSTVAL 0x00000001
#define NFC_FLASH_STATUS1_RSTVAL 0x00000000
#define NFC_FLASH_STATUS2_RSTVAL 0x00000000
#define NFC_DMA1_ADDR_RSTVAL 0x00000000
#define NFC_DMA2_ADDR_RSTVAL 0x00000000
#define NFC_DMA_CONFIG_RSTVAL 0x00000000
#define NFC_CACHE_SWAP_RSTVAL 0x0FFE0FFE
#define NFC_SECTOR_SIZE_RSTVAL 0x00000420
#define NFC_FLASH_CONFIG_RSTVAL 0x000EA631
#define NFC_IRQ_STATUS_RSTVAL 0x04000000
/***************** Module-Relative Register Mask *************************/
/* NFC_FLASH_CMD1 Field */
#define CMD1_MASK 0xFFFF0000
#define CMD1_SHIFT 0
#define CMD_BYTE2_MASK 0xFF000000
#define CMD_BYTE2_SHIFT 24
#define CMD_BYTE3_MASK 0x00FF0000
#define CMD_BYTE3_SHIFT 16
/* NFC_FLASH_CM2 Field */
#define CMD2_MASK 0xFFFFFF07
#define CMD2_SHIFT 0
#define CMD_BYTE1_MASK 0xFF000000
#define CMD_BYTE1_SHIFT 24
#define CMD_CODE_MASK 0x00FFFF00
#define CMD_CODE_SHIFT 8
#define BUFNO_MASK 0x00000006
#define BUFNO_SHIFT 1
#define BUSY_MASK 0x00000001
#define BUSY_SHIFT 0
#define START_MASK 0x00000001
#define START_SHIFT 0
/* NFC_COL_ADDR Field */
#define COL_ADDR_MASK 0x0000FFFF
#define COL_ADDR_SHIFT 0
#define COL_ADDR_COL_ADDR2_MASK 0x0000FF00
#define COL_ADDR_COL_ADDR2_SHIFT 8
#define COL_ADDR_COL_ADDR1_MASK 0x000000FF
#define COL_ADDR_COL_ADDR1_SHIFT 0
/* NFC_ROW_ADDR Field */
#define ROW_ADDR_MASK 0x00FFFFFF
#define ROW_ADDR_SHIFT 0
#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
#define ROW_ADDR_CHIP_SEL_SHIFT 24
#define ROW_ADDR_ROW_ADDR3_MASK 0x00FF0000
#define ROW_ADDR_ROW_ADDR3_SHIFT 16
#define ROW_ADDR_ROW_ADDR2_MASK 0x0000FF00
#define ROW_ADDR_ROW_ADDR2_SHIFT 8
#define ROW_ADDR_ROW_ADDR1_MASK 0x000000FF
#define ROW_ADDR_ROW_ADDR1_SHIFT 0
/* NFC_FLASH_COMMAND_REPEAT Field */
#define COMMAND_REPEAT_MASK 0x0000FFFF
#define COMMAND_REPEAT_SHIFT 0
#define COMMAND_REPEAT_REPEAT_COUNT_MASK 0x0000FFFF
#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT 0
/* NFC_ROW_ADDR_INC Field */
#define ROW_ADDR_INC_MASK 0x00FFFFFF
#define ROW_ADDR_INC_SHIFT 0
#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK 0x00FF0000
#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT 16
#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK 0x0000FF00
#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT 8
#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK 0x000000FF
#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT 0
/* NFC_FLASH_STATUS1 Field */
#define STATUS1_MASK 0xFFFFFFFF
#define STATUS1_SHIFT 0
#define STATUS1_ID_BYTE1_MASK 0xFF000000
#define STATUS1_ID_BYTE1_SHIFT 24
#define STATUS1_ID_BYTE2_MASK 0x00FF0000
#define STATUS1_ID_BYTE2_SHIFT 16
#define STATUS1_ID_BYTE3_MASK 0x0000FF00
#define STATUS1_ID_BYTE3_SHIFT 8
#define STATUS1_ID_BYTE4_MASK 0x000000FF
#define STATUS1_ID_BYTE4_SHIFT 0
/* NFC_FLASH_STATUS2 Field */
#define STATUS2_MASK 0xFF0000FF
#define STATUS2_SHIFT 0
#define STATUS2_ID_BYTE5_MASK 0xFF000000
#define STATUS2_ID_BYTE5_SHIFT 24
#define STATUS_BYTE1_MASK 0x000000FF
#define STATUS2_STATUS_BYTE1_SHIFT 0
/* NFC_DMA1_ADDR Field */
#define DMA1_ADDR_MASK 0xFFFFFFFF
#define DMA1_ADDR_SHIFT 0
#define DMA1_ADDR_DMA1_ADDR_MASK 0xFFFFFFFF
#define DMA1_ADDR_DMA1_ADDR_SHIFT 0
/* DMA2_ADDR Field */
#define DMA2_ADDR_MASK 0xFFFFFFFF
#define DMA2_ADDR_SHIFT 0
#define DMA2_ADDR_DMA2_ADDR_MASK 0xFFFFFFFF
#define DMA2_ADDR_DMA2_ADDR_SHIFT 0
/* DMA_CONFIG Field */
#define DMA_CONFIG_MASK 0xFFFFFFFF
#define DMA_CONFIG_SHIFT 0
#define DMA_CONFIG_DMA1_CNT_MASK 0xFFF00000
#define DMA_CONFIG_DMA1_CNT_SHIFT 20
#define DMA_CONFIG_DMA2_CNT_MASK 0x000FE000
#define DMA_CONFIG_DMA2_CNT_SHIFT 13
#define DMA_CONFIG_DMA2_OFFSET_MASK 0x00001FC0
#define DMA_CONFIG_DMA2_OFFSET_SHIFT 2
#define DMA_CONFIG_DMA1_ACT_MASK 0x00000002
#define DMA_CONFIG_DMA1_ACT_SHIFT 1
#define DMA_CONFIG_DMA2_ACT_MASK 0x00000001
#define DMA_CONFIG_DMA2_ACT_SHIFT 0
/* NFC_CACHE_SWAP Field */
#define CACHE_SWAP_MASK 0x0FFE0FFE
#define CACHE_SWAP_SHIFT 1
#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK 0x0FFE0000
#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT 17
#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK 0x00000FFE
#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT 1
/* NFC_SECTOR_SIZE Field */
#define SECTOR_SIZE_MASK 0x00001FFF
#define SECTOR_SIZE_SHIFT 0
#define SECTOR_SIZE_SECTOR_SIZE_MASK 0x00001FFF
#define SECTOR_SIZE_SECTOR_SIZE_SHIFT 0
/* NFC_FLASH_CONFIG Field */
#define CONFIG_MASK 0xFFFFFFFF
#define CONFIG_SHIFT 0
#define CONFIG_STOP_ON_WERR_MASK 0x80000000
#define CONFIG_STOP_ON_WERR_SHIFT 31
#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
#define CONFIG_ECC_SRAM_REQ_MASK 0x00200000
#define CONFIG_ECC_SRAM_REQ_SHIFT 21
#define CONFIG_DMA_REQ_MASK 0x00100000
#define CONFIG_DMA_REQ_SHIFT 20
#define CONFIG_ECC_MODE_MASK 0x000E0000
#define CONFIG_ECC_MODE_SHIFT 17
#define CONFIG_FAST_FLASH_MASK 0x00010000
#define CONFIG_FAST_FLASH_SHIFT 16
#define CONFIG_ID_COUNT_MASK 0x0000E000
#define CONFIG_ID_COUNT_SHIFT 13
#define CONFIG_CMD_TIMEOUT_MASK 0x00001F00
#define CONFIG_CMD_TIMEOUT_SHIFT 8
#define CONFIG_16BIT_MASK 0x00000080
#define CONFIG_16BIT_SHIFT 7
#define CONFIG_BOOT_MODE_MASK 0x00000040
#define CONFIG_BOOT_MODE_SHIFT 6
#define CONFIG_ADDR_AUTO_INCR_MASK 0x00000020
#define CONFIG_ADDR_AUTO_INCR_SHIFT 5
#define CONFIG_BUFNO_AUTO_INCR_MASK 0x00000010
#define CONFIG_BUFNO_AUTO_INCR_SHIFT 4
#define CONFIG_PAGE_CNT_MASK 0x0000000F
#define CONFIG_PAGE_CNT_SHIFT 0
/* NFC_IRQ_STATUS Field */
#define MASK 0xEFFC003F
#define SHIFT 0
#define WERR_IRQ_MASK 0x80000000
#define WERR_IRQ_SHIFT 31
#define CMD_DONE_IRQ_MASK 0x40000000
#define CMD_DONE_IRQ_SHIFT 30
#define IDLE_IRQ_MASK 0x20000000
#define IDLE_IRQ_SHIFT 29
#define WERR_STATUS_MASK 0x08000000
#define WERR_STATUS_SHIFT 27
#define FLASH_CMD_BUSY_MASK 0x04000000
#define FLASH_CMD_BUSY_SHIFT 26
#define RESIDUE_BUSY_MASK 0x02000000
#define RESIDUE_BUSY_SHIFT 25
#define ECC_BUSY_MASK 0x01000000
#define ECC_BUSY_SHIFT 24
#define DMA_BUSY_MASK 0x00800000
#define DMA_BUSY_SHIFT 23
#define WERR_EN_MASK 0x00400000
#define WERR_EN_SHIFT 22
#define CMD_DONE_EN_MASK 0x00200000
#define CMD_DONE_EN_SHIFT 21
#define IDLE_EN_MASK 0x00100000
#define IDLE_EN_SHIFT 20
#define WERR_CLEAR_MASK 0x00080000
#define WERR_CLEAR_SHIFT 19
#define CMD_DONE_CLEAR_MASK 0x00040000
#define CMD_DONE_CLEAR_SHIFT 18
#define IDLE_CLEAR_MASK 0x00020000
#define IDLE_CLEAR_SHIFT 17
#define RESIDUE_BUFF_NO_MASK 0x00000030
#define RESIDUE_BUFF_NO_SHIFT 4
#define ECC_BUFF_NO_MASK 0x000000C0
#define ECC_BUFF_NO_SHIFT 2
#define DMA_BUFF_NO_MASK 0x00000003
#endif /* MPC5125_NFC_H */
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