summaryrefslogtreecommitdiff
path: root/board/syteco/jadecpu/lowlevel_init.S
blob: 5ad4dceb92414659e1ffe828f74ae3b5655c340d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
/*
 * Board specific setup info
 *
 * (C) Copyright 2007, mycable GmbH
 * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
 *
 * (C) Copyright 2003, ARM Ltd.
 * Philippe Robin, <philippe.robin@arm.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/macro.h>
#include <asm/arch/mb86r0x.h>
#include <asm/arch/asm-offsets.h>

/* Set up the platform, once the cpu has been initialized */
.globl lowlevel_init
lowlevel_init:
/*
 * Initialize Clock Reset Generator (CRG)
 */

	ldr		r0, =MB86R0x_CRG_BASE

	/* Not change the initial value that is set by external pin.*/
WAIT_PLL:
	ldr		r2, [r0, #CRG_CRPR]	/* Wait for PLLREADY */
	tst		r2, #MB86R0x_CRG_CRPR_PLLRDY
	beq		WAIT_PLL

	/* Set clock gate control */
	ldr		r1, =CONFIG_SYS_CRG_CRHA_INIT
	str		r1, [r0, #CRG_CRHA]
	ldr		r1, =CONFIG_SYS_CRG_CRPA_INIT
	str		r1, [r0, #CRG_CRPA]
	ldr		r1, =CONFIG_SYS_CRG_CRPB_INIT
	str		r1, [r0, #CRG_CRPB]
	ldr		r1, =CONFIG_SYS_CRG_CRHB_INIT
	str		r1, [r0, #CRG_CRHB]
	ldr		r1, =CONFIG_SYS_CRG_CRAM_INIT
	str		r1, [r0, #CRG_CRAM]

/*
 * Initialize External Bus Interface
 */
	ldr		r0, =MB86R0x_MEMC_BASE

	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
	str		r1, [r0, #MEMC_MCFMODE0]
	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
	str		r1, [r0, #MEMC_MCFMODE2]
	ldr		r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
	str		r1, [r0, #MEMC_MCFMODE4]

	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
	str		r1, [r0, #MEMC_MCFTIM0]
	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
	str		r1, [r0, #MEMC_MCFTIM2]
	ldr		r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
	str		r1, [r0, #MEMC_MCFTIM4]

	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
	str		r1, [r0, #MEMC_MCFAREA0]
	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
	str		r1, [r0, #MEMC_MCFAREA2]
	ldr		r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
	str		r1, [r0, #MEMC_MCFAREA4]

/*
 * Initialize DDR2 Controller
 */

	/* Wait for PLL LOCK up time or more */
	wait_timer	20

	/*
	 * (2) Initialize DDRIF
	 */
	ldr	r0, =MB86R0x_DDR2_BASE
	ldr	r1, =CONFIG_SYS_DDR2_DRIMS_INIT
	strh	r1, [r0, #DDR2_DRIMS]

	/*
	 * (3) Wait for 20MCKPs(120nsec) or more
	 */
	wait_timer	20

	/*
	 * (4) IRESET/IUSRRST release
	 */
	ldr	r0, =MB86R0x_CCNT_BASE
	ldr	r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
	str	r1, [r0, #CCNT_CDCRC]

	/*
	 * (5) Wait for 20MCKPs(120nsec) or more
	 */
	wait_timer	20

	/*
	 * (6) IDLLRST release
	 */
	ldr	r0, =MB86R0x_CCNT_BASE
	ldr	r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
	str	r1, [r0, #CCNT_CDCRC]

	/*
	 * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
	 */
	wait_timer	33536

	/*
	 * (9) MCKE ON
	 */
	ldr	r0, =MB86R0x_DDR2_BASE
	ldr	r1, =CONFIG_SYS_DDR2_DRIC1_INIT
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_DRIC2_INIT
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =CONFIG_SYS_DDR2_DRCA_INIT
	strh	r1, [r0, #DDR2_DRCA]
	ldr	r1, =MB86R0x_DDR2_DRCI_INIT
	strh	r1, [r0, #DDR2_DRIC]

	/*
	 * (10) Initialize SDRAM
	 */

	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	wait_timer	67			/* 400ns wait */

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	wait_timer 200

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	wait_timer	18			/* 105ns wait */

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	wait_timer	200			/* MRS to OCD: 200clock */

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
	strh	r1, [r0, #DDR2_DRIC1]
	ldr	r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
	strh	r1, [r0, #DDR2_DRIC2]
	ldr	r1, =MB86R0x_DDR2_DRCI_CMD
	strh	r1, [r0, #DDR2_DRIC]

	ldr	r1, =CONFIG_SYS_DDR2_DRCM_INIT
	strh	r1, [r0, #DDR2_DRCM]

	ldr	r1, =CONFIG_SYS_DDR2_DRCST1_INIT
	strh	r1, [r0, #DDR2_DRCST1]

	ldr	r1, =CONFIG_SYS_DDR2_DRCST2_INIT
	strh	r1, [r0, #DDR2_DRCST2]

	ldr	r1, =CONFIG_SYS_DDR2_DRCR_INIT
	strh	r1, [r0, #DDR2_DRCR]

	ldr	r1, =CONFIG_SYS_DDR2_DRCF_INIT
	strh	r1, [r0, #DDR2_DRCF]

	ldr	r1, =CONFIG_SYS_DDR2_DRASR_INIT
	strh	r1, [r0, #DDR2_DRASR]

	/*
	 * (11) ODT setting
	 */
	ldr	r1, =CONFIG_SYS_DDR2_DROBS_INIT
	strh	r1, [r0, #DDR2_DROBS]
	ldr	r1, =CONFIG_SYS_DDR2_DROABA_INIT
	strh	r1, [r0, #DDR2_DROABA]
	ldr	r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
	strh	r1, [r0, #DDR2_DRIBSODT1]

	/*
	 * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
	 */
	ldr	r1, =CONFIG_SYS_DDR2_DROS_INIT
	strh	r1, [r0, #DDR2_DROS]
	ldr	r1, =MB86R0x_DDR2_DRCI_NORMAL
	strh	r1, [r0, #DDR2_DRIC]

	mov pc, lr