// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2020 NXP */ /dts-v1/; #include #include "imx8mn.dtsi" / { model = "NXP i.MX8MNano LPDDR4 Audio board 2.0"; compatible = "fsl,imx8mn-ab2", "fsl,imx8mn"; chosen { bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <100>; off-on-delay-us = <12000>; }; reg_ab2_ana_pwr: regulator-ab2-ana-pwr { compatible = "regulator-fixed"; reg = <2>; regulator-name = "ANA_12V0"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ab2_ana_pwr>; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "VDD_5V0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; regulator-always-on; regulator-boot-on; enable-active-high; }; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx8mn-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 >; }; pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_i2c1_gpio: i2c1grp-gpio { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 >; }; pinctrl_i2c2_gpio: i2c2grp-gpio { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 >; }; pinctrl_i2c3_gpio: i2c3grp-gpio { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 >; }; pinctrl_pmic: pmicirq { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; pinctrl_ab2_ana_pwr: ab2anapwrgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 >; }; pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 >; }; pinctrl_uart2: uart1grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 >; }; pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; pinctrl_mipi_dsi_en: mipi_dsi_en { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 >; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: pca9450@25 { reg = <0x25>; compatible = "nxp,pca9450b"; /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { #address-cells = <1>; #size-cells = <0>; pca9450,pmic-buck2-uses-i2c-dvs; /* Run/Standby voltage */ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; buck1_reg: regulator@0 { reg = <0>; regulator-compatible = "buck1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck2_reg: regulator@1 { reg = <1>; regulator-compatible = "buck2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck3_reg: regulator@2 { reg = <2>; regulator-compatible = "buck3"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; buck4_reg: regulator@3 { reg = <3>; regulator-compatible = "buck4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck5_reg: regulator@4 { reg = <4>; regulator-compatible = "buck5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; buck6_reg: regulator@5 { reg = <5>; regulator-compatible = "buck6"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: regulator@6 { reg = <6>; regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo2_reg: regulator@7 { reg = <7>; regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; ldo3_reg: regulator@8 { reg = <8>; regulator-compatible = "ldo3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo4_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo4"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; ldo5_reg: regulator@10 { reg = <10>; regulator-compatible = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; }; &i2c2 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; ptn5150: tcpc@1d { compatible = "nxp,ptn5150"; reg = <0x1d>; status = "okay"; port { typec1_dr_sw: endpoint { remote-endpoint = <&usb1_drd_sw>; }; }; typec1_con: connector { compatible = "usb-c-connector"; label = "USB-C"; power-role = "dual"; data-role = "dual"; try-power-role = "sink"; source-pdos = ; sink-pdos = ; op-sink-microwatt = <15000000>; self-powered; }; }; }; &i2c3 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_gpio>; scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; status = "okay"; flash0: mt25qu256aba@0 { reg = <0>; compatible = "jedec,spi-nor"; spi-max-frequency = <80000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; }; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; phy-reset-post-delay = <150>; phy-reset-duration = <10>; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; eee-broken-1000t; }; }; }; &snvs_pwrkey { status = "okay"; }; &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &usbotg1 { picophy,pre-emp-curr-control = <3>; picophy,dc-vol-level-adjust = <7>; dr_mode = "host"; hnp-disable; srp-disable; adp-disable; usb-role-switch; status = "okay"; port { usb1_drd_sw: endpoint { remote-endpoint = <&typec1_dr_sw>; }; }; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; };