From d85e2f7e59605836d899a289c58d8bce60e2b41d Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 28 May 2014 17:16:00 +0200 Subject: apalis-imx6: use UARTs in DCE mode The Apalis standart uses the UART in DTE mode. This commit uses UART1 in DTE mode for the U-Boot console and configures all used UARTs to start in DTE mode. Note that for this to work module version V1.0A requires TXD/RXD to be crossed between the Apalis iMX6 and the RS232 transceiver. --- board/toradex/apalis_imx6/apalis_imx6.c | 30 +++++++++++++++++++++++------- drivers/serial/serial_mxc.c | 10 +++++++++- include/configs/apalis-imx6.h | 1 + 3 files changed, 33 insertions(+), 8 deletions(-) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index c4afd9fea2..305783badc 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -83,14 +83,13 @@ int dram_init(void) /* Apalis UART1 */ iomux_v3_cfg_t const uart1_pads[] = { +#ifndef CONFIG_MXC_UART_DTE MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -/* Apalis UART2 */ -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +#else + MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +#endif }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -258,10 +257,27 @@ iomux_v3_cfg_t const usb_pads[] = { MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +/* if UARTs are used in DTE mode, so switch the mode on all UARTs before + * any pinmuxing connects a (DCE) output to a transceiver output. + */ +#define UFCR 0x90 /* FIFO Control Register */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ +#define SET_DCEDTE(p) (writel( (readl((u32 *) (p)) | UFCR_DCEDTE), (u32 *) (p))) + +static void setup_dtemode_uart(void) +{ + SET_DCEDTE(UART1_BASE + UFCR); + SET_DCEDTE(UART2_BASE + UFCR); + SET_DCEDTE(UART4_BASE + UFCR); + SET_DCEDTE(UART5_BASE + UFCR); +} + static void setup_iomux_uart(void) { +#ifdef CONFIG_MXC_UART_DTE + setup_dtemode_uart(); +#endif imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } #ifdef CONFIG_USB_EHCI_MX6 diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 56bee55208..bfc473bf66 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -96,6 +96,7 @@ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_DCEDTE (1<<6) /* DCE=0 */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ @@ -137,7 +138,7 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (__REG(UART_PHYS + UFCR) & ~UFCR_RFDIV) | (4 << 7); /* divide input clock by 2 */ __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); @@ -193,6 +194,13 @@ static int mxc_serial_init(void) __REG(UART_PHYS + UTS) = 0x0; + __REG(UART_PHYS + UFCR) = +#ifdef CONFIG_MXC_UART_DTE + UFCR_DCEDTE; +#else + 0; +#endif + serial_setbrg(); __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; diff --git a/include/configs/apalis-imx6.h b/include/configs/apalis-imx6.h index e1f00e8bb0..f88fa094ca 100644 --- a/include/configs/apalis-imx6.h +++ b/include/configs/apalis-imx6.h @@ -42,6 +42,7 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_MXC_UART_DTE /* use the uart in DTE mode */ /* I2C Configs */ #define CONFIG_CMD_I2C -- cgit v1.2.3