From d0a67d4a4d2e04dbfa2c69066599d7e939cff175 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Fri, 9 Jun 2023 15:58:40 +0200 Subject: arm: dts: k3-am625-verdin-lpddr4-1600MTs: support up to 95 celsius degrees Change memory configurations to operate at temperature of 95 degrees. Currently, dynamic adaptation of temperature related timings is not supported [1] so the config is for the worst timings. It is possibile to do so because LPDDR4 devices are refreshed properly if the memory controller issues REFRESH commands with same or *shorter* refresh period than reported by MR4 OP[2:0] which depend upon device temperature. Configuration is output from SysConfig [2] web tool, currently at version 00.09.08, starting from previous configuration while modifying these temperature related properties: - Operating Temperature Range to "-40C to 95C" - tREFIab (ns) to 1950 - tREFIpb (ns) to 244 - tRASmax (ns) to 17550 [1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1234907/am625-lpddr4-configuration-and-operating-temperature [2] https://dev.ti.com/sysconfig Upstream-Status: Pending Series [3] already send for review with the previous configuration, we'll send afterward or update it in case a V2 is needed. [3] https://lore.kernel.org/all/20230607120639.82087-1-marcel@ziswiler.com/ Related-to: ELB-5200 Signed-off-by: Emanuele Ghidoli --- arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 150 +++++++++++------------ 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index 6b770b63fb..f3b678bad7 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -2,7 +2,7 @@ /* * This file was generated with the * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08 - * Tue Apr 04 2023 14:52:53 GMT+0200 (Central European Summer Time) + * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -60,52 +60,52 @@ #define DDRSS_CTL_42_DATA 0x0000081C #define DDRSS_CTL_43_DATA 0x00000000 #define DDRSS_CTL_44_DATA 0x05000804 -#define DDRSS_CTL_45_DATA 0x00000700 +#define DDRSS_CTL_45_DATA 0x00000B00 #define DDRSS_CTL_46_DATA 0x09090004 -#define DDRSS_CTL_47_DATA 0x00000203 -#define DDRSS_CTL_48_DATA 0x00320007 -#define DDRSS_CTL_49_DATA 0x09090023 -#define DDRSS_CTL_50_DATA 0x0000190F -#define DDRSS_CTL_51_DATA 0x00320007 -#define DDRSS_CTL_52_DATA 0x09090023 -#define DDRSS_CTL_53_DATA 0x0900190F +#define DDRSS_CTL_47_DATA 0x00000204 +#define DDRSS_CTL_48_DATA 0x00370008 +#define DDRSS_CTL_49_DATA 0x09090024 +#define DDRSS_CTL_50_DATA 0x00001910 +#define DDRSS_CTL_51_DATA 0x00370008 +#define DDRSS_CTL_52_DATA 0x09090024 +#define DDRSS_CTL_53_DATA 0x09001910 #define DDRSS_CTL_54_DATA 0x000A0A09 -#define DDRSS_CTL_55_DATA 0x040006DB +#define DDRSS_CTL_55_DATA 0x0400036D #define DDRSS_CTL_56_DATA 0x09092004 #define DDRSS_CTL_57_DATA 0x00000C0A -#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_58_DATA 0x060036D8 #define DDRSS_CTL_59_DATA 0x09092006 #define DDRSS_CTL_60_DATA 0x00000C0A -#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_61_DATA 0x060036D8 #define DDRSS_CTL_62_DATA 0x03042006 -#define DDRSS_CTL_63_DATA 0x04050002 -#define DDRSS_CTL_64_DATA 0x100F100F +#define DDRSS_CTL_63_DATA 0x06050002 +#define DDRSS_CTL_64_DATA 0x10111011 #define DDRSS_CTL_65_DATA 0x01010008 -#define DDRSS_CTL_66_DATA 0x041F1F07 -#define DDRSS_CTL_67_DATA 0x03111103 -#define DDRSS_CTL_68_DATA 0x00001111 +#define DDRSS_CTL_66_DATA 0x0420200A +#define DDRSS_CTL_67_DATA 0x04131304 +#define DDRSS_CTL_68_DATA 0x00001313 #define DDRSS_CTL_69_DATA 0x00000101 #define DDRSS_CTL_70_DATA 0x00000000 #define DDRSS_CTL_71_DATA 0x01000000 #define DDRSS_CTL_72_DATA 0x00130803 -#define DDRSS_CTL_73_DATA 0x000000BB +#define DDRSS_CTL_73_DATA 0x00000059 #define DDRSS_CTL_74_DATA 0x00000130 -#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_75_DATA 0x00000610 #define DDRSS_CTL_76_DATA 0x00000130 -#define DDRSS_CTL_77_DATA 0x00000C28 +#define DDRSS_CTL_77_DATA 0x00000610 #define DDRSS_CTL_78_DATA 0x00000005 #define DDRSS_CTL_79_DATA 0x0000000A -#define DDRSS_CTL_80_DATA 0x00000010 +#define DDRSS_CTL_80_DATA 0x00000004 #define DDRSS_CTL_81_DATA 0x00000098 -#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_82_DATA 0x000000BB #define DDRSS_CTL_83_DATA 0x00000098 -#define DDRSS_CTL_84_DATA 0x0000017E +#define DDRSS_CTL_84_DATA 0x000000BB #define DDRSS_CTL_85_DATA 0x03004000 #define DDRSS_CTL_86_DATA 0x00001201 #define DDRSS_CTL_87_DATA 0x00060005 #define DDRSS_CTL_88_DATA 0x00000006 #define DDRSS_CTL_89_DATA 0x00000000 -#define DDRSS_CTL_90_DATA 0x05121208 +#define DDRSS_CTL_90_DATA 0x05141408 #define DDRSS_CTL_91_DATA 0x05030A05 #define DDRSS_CTL_92_DATA 0x05030C06 #define DDRSS_CTL_93_DATA 0x01030C06 @@ -134,27 +134,27 @@ #define DDRSS_CTL_116_DATA 0x00040003 #define DDRSS_CTL_117_DATA 0x00040005 #define DDRSS_CTL_118_DATA 0x00000000 -#define DDRSS_CTL_119_DATA 0x00002EC0 -#define DDRSS_CTL_120_DATA 0x00002EC0 -#define DDRSS_CTL_121_DATA 0x00002EC0 -#define DDRSS_CTL_122_DATA 0x00002EC0 -#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_119_DATA 0x00001640 +#define DDRSS_CTL_120_DATA 0x00001640 +#define DDRSS_CTL_121_DATA 0x00001640 +#define DDRSS_CTL_122_DATA 0x00001640 +#define DDRSS_CTL_123_DATA 0x00001640 #define DDRSS_CTL_124_DATA 0x00000000 -#define DDRSS_CTL_125_DATA 0x0000051D -#define DDRSS_CTL_126_DATA 0x00030A00 -#define DDRSS_CTL_127_DATA 0x00030A00 -#define DDRSS_CTL_128_DATA 0x00030A00 -#define DDRSS_CTL_129_DATA 0x00030A00 -#define DDRSS_CTL_130_DATA 0x00030A00 +#define DDRSS_CTL_125_DATA 0x0000026F +#define DDRSS_CTL_126_DATA 0x00018400 +#define DDRSS_CTL_127_DATA 0x00018400 +#define DDRSS_CTL_128_DATA 0x00018400 +#define DDRSS_CTL_129_DATA 0x00018400 +#define DDRSS_CTL_130_DATA 0x00018400 #define DDRSS_CTL_131_DATA 0x00000000 -#define DDRSS_CTL_132_DATA 0x00005518 -#define DDRSS_CTL_133_DATA 0x00030A00 -#define DDRSS_CTL_134_DATA 0x00030A00 -#define DDRSS_CTL_135_DATA 0x00030A00 -#define DDRSS_CTL_136_DATA 0x00030A00 -#define DDRSS_CTL_137_DATA 0x00030A00 +#define DDRSS_CTL_132_DATA 0x00002A70 +#define DDRSS_CTL_133_DATA 0x00018400 +#define DDRSS_CTL_134_DATA 0x00018400 +#define DDRSS_CTL_135_DATA 0x00018400 +#define DDRSS_CTL_136_DATA 0x00018400 +#define DDRSS_CTL_137_DATA 0x00018400 #define DDRSS_CTL_138_DATA 0x00000000 -#define DDRSS_CTL_139_DATA 0x00005518 +#define DDRSS_CTL_139_DATA 0x00002A70 #define DDRSS_CTL_140_DATA 0x00000000 #define DDRSS_CTL_141_DATA 0x00000000 #define DDRSS_CTL_142_DATA 0x00000000 @@ -400,31 +400,31 @@ #define DDRSS_CTL_382_DATA 0x03020301 #define DDRSS_CTL_383_DATA 0x04000102 #define DDRSS_CTL_384_DATA 0x1B000004 -#define DDRSS_CTL_385_DATA 0x00000176 +#define DDRSS_CTL_385_DATA 0x000000B2 #define DDRSS_CTL_386_DATA 0x00000200 #define DDRSS_CTL_387_DATA 0x00000200 #define DDRSS_CTL_388_DATA 0x00000200 #define DDRSS_CTL_389_DATA 0x00000200 -#define DDRSS_CTL_390_DATA 0x00000693 -#define DDRSS_CTL_391_DATA 0x00000E9C +#define DDRSS_CTL_390_DATA 0x00000321 +#define DDRSS_CTL_391_DATA 0x000006F4 #define DDRSS_CTL_392_DATA 0x03050202 -#define DDRSS_CTL_393_DATA 0x00250201 -#define DDRSS_CTL_394_DATA 0x00001850 +#define DDRSS_CTL_393_DATA 0x00260201 +#define DDRSS_CTL_394_DATA 0x00000C20 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 #define DDRSS_CTL_397_DATA 0x00000200 #define DDRSS_CTL_398_DATA 0x00000200 -#define DDRSS_CTL_399_DATA 0x00006D68 -#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_399_DATA 0x00003690 +#define DDRSS_CTL_400_DATA 0x00007940 #define DDRSS_CTL_401_DATA 0x070D0402 -#define DDRSS_CTL_402_DATA 0x00250405 -#define DDRSS_CTL_403_DATA 0x00001850 +#define DDRSS_CTL_402_DATA 0x00260405 +#define DDRSS_CTL_403_DATA 0x00000C20 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 -#define DDRSS_CTL_408_DATA 0x00006D68 -#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_408_DATA 0x00003690 +#define DDRSS_CTL_409_DATA 0x00007940 #define DDRSS_CTL_410_DATA 0x070D0402 #define DDRSS_CTL_411_DATA 0x00000405 #define DDRSS_CTL_412_DATA 0x00000000 @@ -606,19 +606,19 @@ #define DDRSS_PI_165_DATA 0x00780078 #define DDRSS_PI_166_DATA 0x00101001 #define DDRSS_PI_167_DATA 0x00000034 -#define DDRSS_PI_168_DATA 0x00000042 -#define DDRSS_PI_169_DATA 0x00020042 +#define DDRSS_PI_168_DATA 0x00000043 +#define DDRSS_PI_169_DATA 0x00020043 #define DDRSS_PI_170_DATA 0x02000200 #define DDRSS_PI_171_DATA 0x00000004 #define DDRSS_PI_172_DATA 0x0000080C #define DDRSS_PI_173_DATA 0x00081C00 #define DDRSS_PI_174_DATA 0x001C0000 #define DDRSS_PI_175_DATA 0x00000013 -#define DDRSS_PI_176_DATA 0x000000BB +#define DDRSS_PI_176_DATA 0x00000059 #define DDRSS_PI_177_DATA 0x00000130 -#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_178_DATA 0x00000610 #define DDRSS_PI_179_DATA 0x00000130 -#define DDRSS_PI_180_DATA 0x04000C28 +#define DDRSS_PI_180_DATA 0x04000610 #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001501 #define DDRSS_PI_183_DATA 0x001D001D @@ -669,28 +669,28 @@ #define DDRSS_PI_228_DATA 0x32120058 #define DDRSS_PI_229_DATA 0x05000101 #define DDRSS_PI_230_DATA 0x00000408 -#define DDRSS_PI_231_DATA 0x05030900 -#define DDRSS_PI_232_DATA 0x00040900 -#define DDRSS_PI_233_DATA 0x0000062B +#define DDRSS_PI_231_DATA 0x05040900 +#define DDRSS_PI_232_DATA 0x00060900 +#define DDRSS_PI_233_DATA 0x00000315 #define DDRSS_PI_234_DATA 0x20010004 #define DDRSS_PI_235_DATA 0x0A0A0A03 -#define DDRSS_PI_236_DATA 0x11090000 -#define DDRSS_PI_237_DATA 0x1009000F -#define DDRSS_PI_238_DATA 0x000062B8 -#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_236_DATA 0x13090000 +#define DDRSS_PI_237_DATA 0x10090011 +#define DDRSS_PI_238_DATA 0x0000315C +#define DDRSS_PI_239_DATA 0x20030024 #define DDRSS_PI_240_DATA 0x0C0A0C0C -#define DDRSS_PI_241_DATA 0x11090000 -#define DDRSS_PI_242_DATA 0x1009000F -#define DDRSS_PI_243_DATA 0x000062B8 -#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_241_DATA 0x13090000 +#define DDRSS_PI_242_DATA 0x10090011 +#define DDRSS_PI_243_DATA 0x0000315C +#define DDRSS_PI_244_DATA 0x20030024 #define DDRSS_PI_245_DATA 0x0C0A0C0C #define DDRSS_PI_246_DATA 0x00000000 -#define DDRSS_PI_247_DATA 0x00000176 -#define DDRSS_PI_248_DATA 0x00000E9C -#define DDRSS_PI_249_DATA 0x00001850 -#define DDRSS_PI_250_DATA 0x0000F320 -#define DDRSS_PI_251_DATA 0x00001850 -#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_247_DATA 0x000000B2 +#define DDRSS_PI_248_DATA 0x000006F4 +#define DDRSS_PI_249_DATA 0x00000C20 +#define DDRSS_PI_250_DATA 0x00007940 +#define DDRSS_PI_251_DATA 0x00000C20 +#define DDRSS_PI_252_DATA 0x00007940 #define DDRSS_PI_253_DATA 0x01360014 #define DDRSS_PI_254_DATA 0x03030136 #define DDRSS_PI_255_DATA 0x00000003 -- cgit v1.2.3